From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6579 invoked by alias); 5 Dec 2005 01:31:13 -0000 Received: (qmail 6572 invoked by uid 22791); 5 Dec 2005 01:31:12 -0000 X-Spam-Check-By: sourceware.org Received: from miranda.se.axis.com (HELO miranda.se.axis.com) (193.13.178.8) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 05 Dec 2005 01:31:11 +0000 Received: from ignucius.se.axis.com (ignucius.se.axis.com [10.83.5.18]) by miranda.se.axis.com (8.12.9/8.12.9/Debian-5local0.1) with ESMTP id jB51UuWN005592; Mon, 5 Dec 2005 02:30:56 +0100 Received: from ignucius.se.axis.com (localhost [127.0.0.1]) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) with ESMTP id jB51UtmC013175; Mon, 5 Dec 2005 02:30:55 +0100 Received: (from hp@localhost) by ignucius.se.axis.com (8.12.8p1/8.12.8/Debian-2woody1) id jB51UttW013171; Mon, 5 Dec 2005 02:30:55 +0100 Date: Mon, 05 Dec 2005 01:31:00 -0000 Message-Id: <200512050130.jB51UttW013171@ignucius.se.axis.com> From: Hans-Peter Nilsson To: brolley@redhat.com CC: hans-peter.nilsson@axis.com, cgen@sourceware.org, jimb@redhat.com In-reply-to: <43909CD6.2090508@redhat.com> (message from Dave Brolley on Fri, 02 Dec 2005 14:13:26 -0500) Subject: Re: Unbreak CRIS sim: fix -gen-decode-insn-entry. And why the widened mem fetch? Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2005-q4/txt/msg00048.txt.bz2 > Date: Fri, 02 Dec 2005 14:13:26 -0500 > From: Dave Brolley > The switch generator stops when it has tested enough bits to resolve > ambiguity among the defined insns, but since it wasn't going on to test > the remaining bits, the decoder was recognizing invalid insns as valid. > This additional test goes on to test all the fixed bits in each insn to > ensure that they are all correct. I assume you mean with opcode definitions for opcode= 0?0 1?0 (where opcode & 2 is don't care and opcode & 1 is invalid) that there was *before* the extra generated code, only a test generated for (opcode & 4) and that there's *now* (opcode & 5) == 4 and (opcode & 5) == 0, with 1 and 5 flagged as invalid insns; not that you mean that there are now checks for (opcode & 7) == 0 and (opcode & 7) == 4. > It does appear that we could be > smarter about generating the test, however. In this case the tests > appear to be redundant. We could probably add some logic to test only > the untested bits and to not generate the additional test at all if all > of the bits have already been tested. Recent GCC should optimize out any obviously redundant tests with if-tests that are covered by an outer switch/case. Anyway, I briefly tested timing before/after a regened sim/cris, and time difference seems to be in the noise, at least for the test programs I used. I guess most interesting codes fit nicely in the scache or something. So I'm only worried about correctness with the widened opcode fetches and the opcode checks as above. > >The change below mimics the test in > >sim-decode.scm:-gen-decode-fn where entire_insn is conditionally > >declared as a parameter to @prefix@_decode. > This change looks ok to me. Please commit it. Done, thanks. brgds, H-P