From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23236 invoked by alias); 2 Jul 2009 12:29:14 -0000 Received: (qmail 23226 invoked by uid 22791); 2 Jul 2009 12:29:14 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,SPF_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 02 Jul 2009 12:29:05 +0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n62CT1VQ018197; Thu, 2 Jul 2009 08:29:01 -0400 Received: from fche.csb (vpn-10-134.bos.redhat.com [10.16.10.134]) by int-mx1.corp.redhat.com (8.13.1/8.13.1) with ESMTP id n62CT180003270; Thu, 2 Jul 2009 08:29:01 -0400 Received: by fche.csb (Postfix, from userid 2569) id CEC1E58489; Thu, 2 Jul 2009 08:29:00 -0400 (EDT) Date: Thu, 02 Jul 2009 12:29:00 -0000 From: "Frank Ch. Eigler" To: Doug Evans Cc: Joseph A , cgen@sourceware.org Subject: Re: how can one achieve pipelined operation? Message-ID: <20090702122900.GI32510@redhat.com> References: <24210860.post@talk.nabble.com> <20090701105032.GA13767@redhat.com> <4A4C23E6.60401@sebabeach.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A4C23E6.60401@sebabeach.org> User-Agent: Mutt/1.4.2.2i X-IsSubscribed: yes Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2009-q3/txt/msg00004.txt.bz2 HI - On Wed, Jul 01, 2009 at 08:05:10PM -0700, Doug Evans wrote: > [...] > >An exposed pipeline is reasonably easily modelled with deferred write > >queues in a sid-based simulator; see the mep port. > > Thanks. The semantics for each instruction are generated from cgen, > but the pipeline (i.e. instruction fetch, execute, retire) is handcrafted. > [Right?] We have not had to model some details of an ordinary interlocked pipeline (e.g., a separate "fetch" stage) since they do not affect the visible execution of a normal program, only performance. For cycle counting purposes, cgen has some support (functional unit parametrization), though by nature simple counting models are gross exaggerations of real complex CPUs. For unusual pipelines where some interlocks were missing (so a "write" of some sort in one pipeline stage could be briefly invisible to a "read" in another functional unit), assembly programs *are* exposed to the operation of the pipeline. So, in sid, the deferred-write-queue mechanism was built to model that, as driven by the (delay N (set ... ...)) directive in cgen semantics. I don't know which of these two different aspects you need. - FChE