From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 2903 invoked by alias); 12 Jul 2009 02:27:35 -0000 Received: (qmail 2889 invoked by uid 22791); 12 Jul 2009 02:27:35 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,SPF_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 12 Jul 2009 02:27:29 +0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n6C2ROpj025683; Sat, 11 Jul 2009 22:27:24 -0400 Received: from fche.csb (vpn-10-134.bos.redhat.com [10.16.10.134]) by int-mx1.corp.redhat.com (8.13.1/8.13.1) with ESMTP id n6C2RLNG026836; Sat, 11 Jul 2009 22:27:21 -0400 Received: by fche.csb (Postfix, from userid 2569) id 3AB8258463; Sat, 11 Jul 2009 22:27:17 -0400 (EDT) Date: Sun, 12 Jul 2009 02:27:00 -0000 From: "Frank Ch. Eigler" To: Joseph A Cc: cgen@sourceware.org Subject: Re: how can one achieve pipelined operation? Message-ID: <20090712022717.GB2347@redhat.com> References: <24210860.post@talk.nabble.com> <20090701105032.GA13767@redhat.com> <4A4C23E6.60401@sebabeach.org> <20090702122900.GI32510@redhat.com> <24310149.post@talk.nabble.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <24310149.post@talk.nabble.com> User-Agent: Mutt/1.4.2.2i X-IsSubscribed: yes Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2009-q3/txt/msg00019.txt.bz2 Hi - On Thu, Jul 02, 2009 at 09:44:54AM -0700, Joseph A wrote: > As was suggested I have been trying to implement a pipeline with the (delay N > (set ... ...)) directive using the directions given in the [RFA:] Fix > breakage of manually building SID CPU thread, however my port has multiple > ISAs. OK. > I get two errors which say "error: invalid initialization of > reference of type '%ISA1%::write_stacks&' from expression of type > '%CPU%::write_stacks'" and "error: invalid initialization of > reference of type '%ISA2%::write_stacks&' from expression of type > '%CPU%::write_stacks'". Also, the machine generated reset() and > writeback() functions are empty. These don't sound familiar to me. I can only advise that you refer to the sid simulator pieces generated & hand-written for other exposed-pipeline ports (mt, sh/*). - FChE