From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 21345 invoked by alias); 23 Nov 2009 01:03:59 -0000 Received: (qmail 21185 invoked by uid 22791); 23 Nov 2009 01:03:58 -0000 X-SWARE-Spam-Status: No, hits=-0.5 required=5.0 tests=AWL,BAYES_00,DNS_FROM_RFC_BOGUSMX X-Spam-Check-By: sourceware.org Received: from sebabeach.org (HELO sebabeach.org) (64.165.110.50) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 23 Nov 2009 01:02:55 +0000 Received: by sebabeach.org (Postfix, from userid 500) id 04E476E3DE; Sun, 22 Nov 2009 17:02:53 -0800 (PST) From: Doug Evans To: cgen@sourceware.org Subject: [commit] support for instruction with words > 32 bits Message-Id: <20091123010254.04E476E3DE@sebabeach.org> Date: Mon, 23 Nov 2009 01:03:00 -0000 X-IsSubscribed: yes Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2009-q4/txt/msg00041.txt.bz2 Hi. This patch adds beginnings for support for instructions with words > 32 bits. [e.g. for architectures where it's preferable to record insns in 64 bits ints] 2009-11-22 Doug Evans * mach.scm (): New member large-insn-word?. (/adata-set-derived!): Set it. (adata-large-insn-word?): New function. * sim-arch.scm (/gen-cpuall-includes): Don't #include cgen-engine.h here. * sim-cpu.scm (cgen-cpu.h): #include it here. (/gen-cpu-defines): Define CGEN_INSN_WORD. (/gen-no-scache-semantic-fn): Use CGEN_INSN_WORD instead of CGEN_INSN_INT. * sim-decode.scm (/gen-idesc-decls): Ditto. (/gen-extract-case, /gen-decode-fn): Ditto. * sim-model.scm (/gen-model-insn-fn): Ditto. * sim.scm (gen-argbuf-type): Ditto.