Hello,

Just to remind, I'm trying to do a cgen-based m68hc08 description.
Currently I've stumbled upon sim insn decoder. All the extract_ifmt_*
parts of @cpu@_decode expect to have entire insn bits in entire_insn
aligned to the LSB bit of that value. The problem is that
instructions of my MCU are of variable length and I use lsb0=#f setting.

I found two solutions for my case:
* First one is to teach extract() part of mloop.in more details about
  insn lengths, so that it finds on it's own what is the length of the
  insn and pushes the correct entire_insn to @cpu@_decode.

  I find this pre-parsing clumsy and unclean.

* Another one is to change the API of @cpu@_decode to require
  entire_insn to be msb-aligned if the ISA is lsb0=#f.

  The patch is really simple (see attach), however it can (and most
  probably will) break other lsb0=#f arches (m32r/m32c).

Could you please comment on this topic?

-- 
With best wishes
Dmitry