From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16064 invoked by alias); 28 Dec 2009 23:47:01 -0000 Received: (qmail 16055 invoked by uid 22791); 28 Dec 2009 23:47:01 -0000 X-SWARE-Spam-Status: No, hits=-2.0 required=5.0 tests=BAYES_00,RCVD_IN_SORBS_WEB,SPF_PASS X-Spam-Check-By: sourceware.org Received: from ey-out-1920.google.com (HELO ey-out-1920.google.com) (74.125.78.150) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 28 Dec 2009 23:46:57 +0000 Received: by ey-out-1920.google.com with SMTP id 4so2720674eyg.42 for ; Mon, 28 Dec 2009 15:46:55 -0800 (PST) Received: by 10.216.89.82 with SMTP id b60mr5745786wef.170.1262044015111; Mon, 28 Dec 2009 15:46:55 -0800 (PST) Received: from doriath.ww600.siemens.net (ppp89-110-12-159.pppoe.avangarddsl.ru [89.110.12.159]) by mx.google.com with ESMTPS id 5sm31438610eyf.10.2009.12.28.15.46.53 (version=SSLv3 cipher=RC4-MD5); Mon, 28 Dec 2009 15:46:54 -0800 (PST) Date: Mon, 28 Dec 2009 23:47:00 -0000 From: Dmitry Eremin-Solenikov To: cgen@sourceware.org Subject: Problem in cgen-generated sim insn decoder. Message-ID: <20091228234650.GA9733@doriath.ww600.siemens.net> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="bp/iNruPH9dso1Pn" Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2009-q4/txt/msg00055.txt.bz2 --bp/iNruPH9dso1Pn Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-length: 943 Hello, Just to remind, I'm trying to do a cgen-based m68hc08 description. Currently I've stumbled upon sim insn decoder. All the extract_ifmt_* parts of @cpu@_decode expect to have entire insn bits in entire_insn aligned to the LSB bit of that value. The problem is that instructions of my MCU are of variable length and I use lsb0=#f setting. I found two solutions for my case: * First one is to teach extract() part of mloop.in more details about insn lengths, so that it finds on it's own what is the length of the insn and pushes the correct entire_insn to @cpu@_decode. I find this pre-parsing clumsy and unclean. * Another one is to change the API of @cpu@_decode to require entire_insn to be msb-aligned if the ISA is lsb0=#f. The patch is really simple (see attach), however it can (and most probably will) break other lsb0=#f arches (m32r/m32c). Could you please comment on this topic? -- With best wishes Dmitry --bp/iNruPH9dso1Pn Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="cgen-sim-decode.patch" Content-length: 529 diff --git a/cgen/sim-decode.scm b/cgen/sim-decode.scm index 0c6d48c..42c41ec 100644 --- a/cgen/sim-decode.scm +++ b/cgen/sim-decode.scm @@ -437,7 +437,10 @@ void (string-append " CGEN_INSN_WORD insn = " (if (adata-integral-insn? CURRENT-ARCH) - "entire_insn;\n" + (if (current-arch-insn-lsb0?) + "entire_insn;\n" + (string-append + "entire_insn >> (sizeof(UINT) * 8 - " (number->string (sfmt-length sfmt)) ");\n" )) "base_insn;\n")) "") (gen-define-field-macro sfmt) --bp/iNruPH9dso1Pn--