From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 21152 invoked by alias); 23 Apr 2014 21:34:00 -0000 Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org Received: (qmail 21137 invoked by uid 89); 23 Apr 2014 21:34:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.8 required=5.0 tests=BAYES_50,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 X-HELO: o50314941.outbound-mail.sendgrid.net Received: from o50314941.outbound-mail.sendgrid.net (HELO o50314941.outbound-mail.sendgrid.net) (50.31.49.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with SMTP; Wed, 23 Apr 2014 21:33:58 +0000 Received: by mf182.sendgrid.net with SMTP id mf182.31920.535831C3B Wed, 23 Apr 2014 21:33:55 +0000 (UTC) Received: from openrisc-lab.c.bluecmd0.internal (224.23.148.146.bc.googleusercontent.com [146.148.23.224]) by ismtpd-026 (SG) with ESMTP id 14590826283.1843.e2c73 for ; Wed, 23 Apr 2014 21:33:55 +0000 (GMT) Received: by openrisc-lab.c.bluecmd0.internal (Postfix, from userid 1000) id 8A3F021589; Wed, 23 Apr 2014 21:33:54 +0000 (UTC) From: Christian Svensson Date: Wed, 23 Apr 2014 21:34:00 -0000 Subject: [PATCH] Addons for OpenRISC support To: cgen@sourceware.org Message-Id: <20140423213354.8A3F021589@openrisc-lab.c.bluecmd0.internal> X-SG-EID: 88UOb4C5MKc5sGTE4/kuxmE8PF/m5kU9Jp5xQp+YxGB5Vvp8P6kH+3AheM3b5e4qygysBScyZ1nKN7kr5IrPjdHPZPAhZP/Tuc2UMl0AyP+PuQblyKN3Eg91hnMZG9mgfkudUkfItT7NZXxmp/gad4qSzt2gXIGb23Txnn7sPa8= X-SW-Source: 2014-q2/txt/msg00001.txt.bz2 Hi, We (OpenRISC) have recently begun upstreaming a lot of code. One of the first things is our binutils port which depends on these CGEN modifications. This patch has been living in the OpenRISC CGEN repository since 2012. I would be delighted if it could be merged. I'm submitting this patch but the author is Peter Gavin, one of the co-authors of the binutils port. 2014-04-23 Peter Gavin * sim-arch.scm: define WI, UWI, AI, & IAI using mode:c-type * add mul-o1flag (1's complement unsigned multiply overflow flag) and mul-o2flag (2's complement signed multiply overflow flag) * rtl-c.scm: (rem) add rem (reminder) function (needed for OR1K lf.rem.[sd]) (mul-o1flag) new define-fn (mul-o2flag) ditto * rtx-funcs.scm: (rem) add rem (reminder) function (needed for OR1K lf.rem.[sd]) (mul-o1flag) new drn (mul-o2flag) ditto --- cgen.orig/rtl-c.scm 2010-08-30 16:51:27.000000000 +0000 +++ cgen/rtl-c.scm 2014-01-11 11:53:15.565783879 +0000 @@ -1746,6 +1746,14 @@ (define-fn mul (*estate* options mode s1 s2) (s-binop *estate* "MUL" "*" mode s1 s2) ) +; 1's complement overflow +(define-fn mul-o1flag (*estate* options mode s1 s2) + (s-binop *estate* "MUL1OF" #f mode s1 s2) +) +; 2's complement overflow +(define-fn mul-o2flag (*estate* options mode s1 s2) + (s-binop *estate* "MUL2OF" #f mode s1 s2) +) (define-fn div (*estate* options mode s1 s2) (s-binop *estate* "DIV" "/" mode s1 s2) ) @@ -1758,6 +1766,9 @@ (define-fn umod (*estate* options mode s1 s2) (s-binop *estate* "UMOD" "%" mode s1 s2) ) +(define-fn rem (*estate* options mode s1 s2) + (s-binop *estate* "REM" #f mode s1 s2) +) (define-fn sqrt (*estate* options mode s1) (s-unop *estate* "SQRT" #f mode s1) --- cgen.orig/rtx-funcs.scm 2010-01-25 03:50:43.000000000 +0000 +++ cgen/rtx-funcs.scm 2014-01-11 11:53:15.565783879 +0000 @@ -755,6 +755,20 @@ BINARY #f ) +; 1's complement overflow +(drn (mul-o1flag &options &mode s1 s2) + BI + (OPTIONS ANYINTMODE RTX RTX) (NA NA MATCHEXPR MATCH2) + BINARY + #f +) +; 2's complement overflow +(drn (mul-o2flag &options &mode s1 s2) + BI + (OPTIONS ANYINTMODE RTX RTX) (NA NA MATCHEXPR MATCH2) + BINARY + #f +) ; ??? In non-sim case, ensure s1,s2 is in right C type for right result. ; ??? Need two variants, one that avoids implementation defined situations ; [both host and target], and one that specifies implementation defined @@ -783,6 +797,12 @@ BINARY #f ) +(drn (rem &options &mode s1 s2) + #f + (OPTIONS ANYFLOATMODE RTX RTX) (NA NA MATCHEXPR MATCH2) + BINARY + #f +) ; wip: mixed mode mul/div --- cgen.orig/sim-arch.scm 2009-11-23 00:59:57.000000000 +0000 +++ cgen/sim-arch.scm 2014-01-11 11:53:15.565783879 +0000 @@ -100,10 +100,10 @@ "\n" "#define TARGET_BIG_ENDIAN 1\n\n" ; FIXME ;(gen-mem-macros) - ;"/* FIXME: split into 32/64 parts */\n" - ;"#define WI SI\n" - ;"#define UWI USI\n" - ;"#define AI USI\n\n" + "#define WI " (mode:c-type WI) "\n" + "#define UWI " (mode:c-type UWI) "\n" + "#define AI " (mode:c-type AI) "\n" "\n" + "#define IAI " (mode:c-type IAI) "\n" "\n" /gen-cpuall-defines /gen-support-decls /gen-arch-model-decls