From: "Frank Ch. Eigler" <fche@redhat.com>
To: Christian Eggers <ceggers@gmx.de>
Cc: cgen@sourceware.org
Subject: Re: Non-contiguous opcodes
Date: Sat, 23 Jun 2018 00:24:00 -0000 [thread overview]
Message-ID: <20180623002359.GB11259@redhat.com> (raw)
In-Reply-To: <2495676.YSRq6Q5dSM@zbook-ubuntu>
Hi -
On Thu, Jun 21, 2018 at 09:29:39AM +0200, Christian Eggers wrote:
> [...]
> I would like to port GNU binutils for the NXP i.MX SDMA coprocessor
> (see https://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf,
> page 2682 for instruction set).
Neat.
> In contrast to other ISAs found in the cpu files, the SDMA ISA has it's
> opcode splitted into several variable length field within a fixed size
> 16 bit instruction code:
>
> 00000jjj00000000 <- opcode @ 15 5, 7 8
> 00000jjj00000001 <- opcode @ 15 5, 7 8
> 000000ff00000111 <- opcode @ 15 6, 7 8
> 10aaaaaaaaaaaaaa <- opcode @ 15 2
> 11aaaaaaaaaaaaaa <- opcode @ 15 2
> ...
>
> I've tried to solve this with multi-ifields:
> [...]
Without digging into the ISA deeply, nor the two-decade-old memories,
have you considered not doing it that way? Consider instead treating
the opcode-like subfields separately inside the define-normal-insn.
So ditch the single insn-enum as it is, and instead of:
(define-normal-insn
revblo "Reverse Low Order Bytes" ()
"revblo $r"
(+ OP_REVBLO r)
[...]
)
try:
(define-normal-insn
revblo "Reverse Low Order Bytes" ()
"revblo $r"
(+ (f-op15x5 17) (f-op7x8 0) r)
[...]
)
- FChE
next prev parent reply other threads:[~2018-06-23 0:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-21 7:29 Christian Eggers
2018-06-23 0:24 ` Frank Ch. Eigler [this message]
2018-06-26 4:24 ` Christian Eggers
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