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From: "Frank Ch. Eigler" <fche@redhat.com>
To: Sergey Belyashov <sergey.belyashov@gmail.com>
Cc: cgen@sourceware.org
Subject: Re: Writing .cpu file for Z80
Date: Sun, 23 Feb 2020 00:03:00 -0000	[thread overview]
Message-ID: <20200223000317.GE9795@redhat.com> (raw)
In-Reply-To: <CAOe0RDxr+DiZbYT-S5917xUUmG519n5Ej7MjfSu1FVRM16W8qw@mail.gmail.com>

Hi -

> About sufficies. Short sufficies (.s, .l, .is, .il) should be converted to
> the full one by assembler using ADL (acronim for address & data long) mode
> state, which is set by programmer (command line options or directive
> .assume ADL=1 or .assume ADL=0), so these short sufficies cannot be just
> brutforced...

Aha.  If it were just an operand field, a parser could be stateful and
fill that in.  If it's a whole different opcode prefix/pattern, then
a larger custom parser.  Try things :-)


> Another question. Z80 instruction set uses same mnemonic for completely
> different (comparing to other cpus) instructions:
> LD A,n ; 8-bit load immediate
> LD HL,nn ; 16-bit load immediate
> LD A,(nn) ; 8-bit direct memory load
> LD (IX+5),A ;8-bit indirect indexed memory store
> LD (nn),HL ;16-bit direct memory store...
> Can it cause ASM parser issues?

I believe there is precedent for different addressing modes with the
same mnemonic to result in different opcodes.  Sorry I'm not fresh
enough with the code base to point them out, but there are a couple
of mechanisms.  cgen's assembler / disassembler interfaces are
hookable enough that you can generally make things work even if the
abstract cgen model is not quite enough.

- FChE

  reply	other threads:[~2020-02-23  0:03 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-21 14:51 Sergey Belyashov
2020-02-22 15:11 ` Frank Ch. Eigler
2020-02-22 19:19   ` Sergey Belyashov
2020-02-23  0:03     ` Frank Ch. Eigler [this message]
2020-03-23 21:44 Sergey Belyashov
2020-03-24 21:20 ` Sergey Belyashov

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