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[86.128.12.16]) by smtp.gmail.com with ESMTPSA id a12sm1858659wro.68.2020.05.20.00.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2020 00:28:35 -0700 (PDT) Date: Wed, 20 May 2020 08:28:34 +0100 From: Andrew Burgess To: "Jose E. Marchesi" Cc: cgen@sourceware.org Subject: Re: [PATCH] desc-cpu.scm: support passing the instruction endianness to cgen_cpu_open Message-ID: <20200520072834.GG2242921@embecosm.com> References: <87mu64jdoq.fsf@oracle.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87mu64jdoq.fsf@oracle.com> X-Operating-System: Linux/5.5.17-200.fc31.x86_64 (x86_64) X-Uptime: 08:27:30 up 29 days, 21:12, X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: cgen@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Cgen mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 May 2020 07:28:38 -0000 * Jose E. Marchesi via Cgen [2020-05-19 14:45:41 +0200]: > > Hi people! > > This patch adds support for specifying the "instruction endianness" (as > oppossed to data endianness) when calling cgen_cpu_open. > > This is part of a bigger work to properly support arches like BPF, where > the endianness of the instruction is different to the endianness of the > contents of the instruction's fields. > > The accompanying patch for opcodes will be sent to > binutils@sourceware.org today. This CGEN patch will have to be applied > first though. > > OK for master? I'm not a maintainer so can't approve the patch, but for what it's worth, this looks good to me. Thanks, Andrew > > 2020-05-19 Jose E. Marchesi > > * desc-cpu.scm (/gen-cpu-open): Support passing the instruction > endianness to cgen_cpu_open. > > > diff --git a/desc-cpu.scm b/desc-cpu.scm > index b24c9f2..e00d8cd 100644 > --- a/desc-cpu.scm > +++ b/desc-cpu.scm > @@ -788,6 +788,7 @@ static void > CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr > CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name > CGEN_CPU_OPEN_ENDIAN: specify endian choice > + CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice > CGEN_CPU_OPEN_END: terminates arguments > > ??? Simultaneous multiple isas might not make sense, but it's not (yet) > @@ -801,6 +802,7 @@ CGEN_CPU_DESC > CGEN_BITSET *isas = 0; /* 0 = \"unspecified\" */ > unsigned int machs = 0; /* 0 = \"unspecified\" */ > enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; > + enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN; > va_list ap; > > if (! init_p) > @@ -835,6 +837,9 @@ CGEN_CPU_DESC > case CGEN_CPU_OPEN_ENDIAN : > endian = va_arg (ap, enum cgen_endian); > break; > + case CGEN_CPU_OPEN_INSN_ENDIAN : > + insn_endian = va_arg (ap, enum cgen_endian); > + break; > default : > opcodes_error_handler > (/* xgettext:c-format */ > @@ -864,11 +869,8 @@ CGEN_CPU_DESC > cd->isas = cgen_bitset_copy (isas); > cd->machs = machs; > cd->endian = endian; > - /* FIXME: for the sparc case we can determine insn-endianness statically. > - The worry here is where both data and insn endian can be independently > - chosen, in which case this function will need another argument. > - Actually, will want to allow for more arguments in the future anyway. */ > - cd->insn_endian = endian; > + if (insn_endian == CGEN_ENDIAN_UNKNOWN) > + cd->insn_endian = endian; > > /* Table (re)builder. */ > cd->rebuild_tables = @arch@_cgen_rebuild_tables;