From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by sourceware.org (Postfix) with ESMTP id 6ACDC3851C3A for ; Tue, 11 Aug 2020 15:38:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 6ACDC3851C3A Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-63-goVNrYqnObqBD7by9loQEg-1; Tue, 11 Aug 2020 11:38:26 -0400 X-MC-Unique: goVNrYqnObqBD7by9loQEg-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 164D98017F4; Tue, 11 Aug 2020 15:38:25 +0000 (UTC) Received: from redhat.com (ovpn-112-64.phx2.redhat.com [10.3.112.64]) by smtp.corp.redhat.com (Postfix) with ESMTPS id EE25469318; Tue, 11 Aug 2020 15:38:24 +0000 (UTC) Received: from fche by redhat.com with local (Exim 4.94) (envelope-from ) id 1k5WM3-0005Mb-Mf; Tue, 11 Aug 2020 11:38:23 -0400 Date: Tue, 11 Aug 2020 11:38:23 -0400 From: "Frank Ch. Eigler" To: Sergey Belyashov Cc: Sergey Belyashov via Cgen Subject: Re: BUG: non-fixed-length ISAs are unsupported for now Message-ID: <20200811153823.GA20457@redhat.com> References: <20200427162914.GA21677@redhat.com> <87pnbsztze.fsf@gnu.org> <87lfmgzoic.fsf@gnu.org> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.12.0 (2019-05-25) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: cgen@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Cgen mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 11 Aug 2020 15:38:29 -0000 Hi - > Can anybody help me, how to correctly implement Zilog Z80 (and > derivatives) [...] OK. I have no fresh wisdom on this, but: > * 0xCB - next byte is rotation or bit manipulation instruction code, > no optional operands; > * 0xED - next byte is instruction of extended instruction set, > possible 1-2 bytes of immediate operand; > * 0xDD/0xFD - switches use of H, L and HL registers to IX/IY on main > and 0xCB tables (here is difficult, because always added immediate > before instruction code: 0xDD 0xCB 0x07 0x3E - "srl (ix+7)"). .... these sound like they could fit into a single isa. You could have a family of ifields, one set for each of these prefix combinations. (Many could have different names and bit offsets but be otherwise the same.) Then for each instruction, you would have a set of separate define-instruction's for each prefix combination (!), using the corresponding ifields. Ideally, use a cgen macro to generate the separate define-instructions, to factor out the commonalities. > * by all tables> I believe keeping it all in one ISA should make assembler / simulator support rather easier. - FChE