From: "Frank Ch. Eigler" <fche@redhat.com>
To: Sergey Belyashov <sergey.belyashov@gmail.com>
Cc: "Jose E. Marchesi" <jose.marchesi@oracle.com>,
"Frank Ch. Eigler via Cgen" <cgen@sourceware.org>
Subject: Re: BUG: non-fixed-length ISAs are unsupported for now
Date: Wed, 12 Aug 2020 15:57:01 -0400 [thread overview]
Message-ID: <20200812195701.GD27698@redhat.com> (raw)
In-Reply-To: <CAOe0RDxOk0FNcBs3MQaB6w4CEyDnzDuptzP8b0izsgz4icpu6g@mail.gmail.com>
Hi -
> Ok. How to handle variable size instructions then? For example:
> NOP - 0x00
> NEG - 0xed 0x44
> RLC B - 0xcb 0x00
> LD HL, 0x1234 - 0x21 0x34 0x12
> LD IY, 0x1234 - 0xfd 0x21 0x34 0x12
> LD DE, (0x1234) - 0xed 0x5b 0x34 0x12
> RR (IX+9) - 0xdd 0xcb 0x09 0x1e (here 0x09 is 8-bit signed immediate)
Simply, make no change other than setting the base-insn large enough
to contain all the opcode fields. Amongst all these cases, that seems
to be 16 or perhaps 24 bits. I suggest trying 32.
- FChE
next prev parent reply other threads:[~2020-08-12 19:57 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-23 13:37 Sergey Belyashov
2020-04-27 16:29 ` Frank Ch. Eigler
2020-04-27 17:00 ` Sergey Belyashov
2020-04-27 17:52 ` Sergey Belyashov
2020-04-27 18:03 ` Jose E. Marchesi
2020-04-27 19:34 ` Sergey Belyashov
2020-04-27 20:01 ` Jose E. Marchesi
2020-04-27 20:23 ` Sergey Belyashov
2020-04-29 19:11 ` Sergey Belyashov
2020-07-30 9:11 ` Sergey Belyashov
2020-08-11 15:38 ` Frank Ch. Eigler
2020-08-11 15:57 ` Sergey Belyashov
2020-08-11 16:08 ` Frank Ch. Eigler
2020-08-12 13:59 ` Sergey Belyashov
2020-08-12 18:36 ` Frank Ch. Eigler
2020-08-12 18:53 ` Jose E. Marchesi
2020-08-12 19:19 ` Sergey Belyashov
2020-08-12 19:21 ` Frank Ch. Eigler
2020-08-12 19:27 ` Jose E. Marchesi
2020-08-12 19:44 ` Sergey Belyashov
2020-08-12 19:57 ` Frank Ch. Eigler [this message]
2020-08-13 13:34 ` Sergey Belyashov
2020-08-13 14:32 ` Frank Ch. Eigler
2020-08-13 14:47 ` Sergey Belyashov
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