* CGEN: RELAXABLE and RELAX
@ 2000-08-18 9:04 Dave Brolley
2000-08-22 13:33 ` Doug Evans
0 siblings, 1 reply; 2+ messages in thread
From: Dave Brolley @ 2000-08-18 9:04 UTC (permalink / raw)
To: cgen
Hi,
The architecture I'm working with has two load immediate insns
that look syntactically identical except for the range of the
immediate value allowed:
ld Rn,imm8 ; 8 bit immediate
ld Rn,imm16 ; 16 bit immediate
The 8 bit load assembles to a 16 bit insn and the 16 bit load
assembles to a 32 bit insn. From the reading the CGEN manual, it
looks to me like this is what RELAXABLE and RELAX are supposed to
handle. i.e. specifying RELAXABLE on the 8 bit load will cause it
to be tried first during assembly and specifying RELAX on the 16
bit load will cause it to be tried next. I tried this, but when I
code 'ld r1,0x100', I get an error saying bad instruction. 'ld
r1,0xff' assembles correctly. It looks like the 16 bit load was
never considered. Am I missing something?
Thanks,
Dave
^ permalink raw reply [flat|nested] 2+ messages in thread
* CGEN: RELAXABLE and RELAX
2000-08-18 9:04 CGEN: RELAXABLE and RELAX Dave Brolley
@ 2000-08-22 13:33 ` Doug Evans
0 siblings, 0 replies; 2+ messages in thread
From: Doug Evans @ 2000-08-22 13:33 UTC (permalink / raw)
To: Dave Brolley; +Cc: cgen
Dave Brolley writes:
> The architecture I'm working with has two load immediate insns
> that look syntactically identical except for the range of the
> immediate value allowed:
>
> ld Rn,imm8 ; 8 bit immediate
> ld Rn,imm16 ; 16 bit immediate
>
> The 8 bit load assembles to a 16 bit insn and the 16 bit load
> assembles to a 32 bit insn. From the reading the CGEN manual, it
> looks to me like this is what RELAXABLE and RELAX are supposed to
> handle. i.e. specifying RELAXABLE on the 8 bit load will cause it
> to be tried first during assembly and specifying RELAX on the 16
> bit load will cause it to be tried next. I tried this, but when I
> code 'ld r1,0x100', I get an error saying bad instruction. 'ld
> r1,0xff' assembles correctly. It looks like the 16 bit load was
> never considered. Am I missing something?
Hi, you're latest message reminded me I never answered this one.
IIRC, RELAXABLE,RELAX in and of themselves aren't sufficient.
Also, you're definitions of RELAXABLE,RELAX aren't quite correct.
[probably stemming from the documentation]
RELAX: don't try during assembly
From m32r_cgen_assemble_insn:
/* If the RELAX attribute is set, this is an insn that shouldn't be
chosen immediately. Instead, it is used during assembler/linker
relaxation if possible. */
if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
continue;
Also, RELAX/RELAXABLE aren't generally used for this case.
What you do here is specify 8 bit loads a head of 16 bit loads.
The assembler will pick the first applicable one.
[kinda hokey, but sufficient for now]
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2000-08-22 13:33 ` Doug Evans
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