From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15440 invoked by alias); 15 Mar 2006 17:08:03 -0000 Received: (qmail 15432 invoked by uid 22791); 15 Mar 2006 17:08:03 -0000 X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org (qpsmtpd/0.31) with ESMTP; Wed, 15 Mar 2006 17:08:01 +0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.12.11.20060308/8.12.11) with ESMTP id k2FH7wK6029786; Wed, 15 Mar 2006 12:07:58 -0500 Received: from pobox.toronto.redhat.com (pobox.toronto.redhat.com [172.16.14.4]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id k2FH7w114705; Wed, 15 Mar 2006 12:07:58 -0500 Received: from [172.16.14.227] (IDENT:aLcfsNdx3GGvqXB+Dn9U/eRxPg9Wr54r@topaz.toronto.redhat.com [172.16.14.227]) by pobox.toronto.redhat.com (8.12.8/8.12.8) with ESMTP id k2FH7vxX012060; Wed, 15 Mar 2006 12:07:57 -0500 Message-ID: <441849ED.1030503@redhat.com> Date: Wed, 15 Mar 2006 17:08:00 -0000 From: Dave Brolley User-Agent: Mozilla Thunderbird 1.0.2 (X11/20050317) MIME-Version: 1.0 To: Hans-Peter Nilsson CC: cgen@sourceware.org Subject: Re: [RFA:] Fix breakage of manually building SID CPU References: <200603150124.k2F1O5Rk014471@ignucius.se.axis.com> In-Reply-To: <200603150124.k2F1O5Rk014471@ignucius.se.axis.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2006-q1/txt/msg00027.txt.bz2 Hans-Peter Nilsson wrote: >Seems the implementation has introduced a false assumption. >Changing the cris.cpu file with the patch below and retrying as >per previous description I sent, results in: > >./utils-cgen.scm:167:15: In procedure error in expression (apply error (cons # arg)): >./utils-cgen.scm:167:15: delayed operand in a non-parallel cpu: >ABORT: (misc-error) > >So, uh, why would only parallel CPUs have delay-slots? Or do we >actually have differing perceptions and definitions of what a >"delay" is? > It's more of an extension of the notion of what parallel is. The "new" delay implementation (SID only) thinks of a delay as something to be done later, in parallel with something else. I seem to recall that it was intended that delay could be used to implement 1) exposed pipelines 2) delay slots 3) VLIW parallelism It looks like there are no examples of ports which use the "new" delay in the public sources. To make it work, you will need to: 1) Add (parallel-insns 2) to your define-isa to make the error above go away. 2) Generate write.cxx since the "new" delay uses the write stacks which are generated there. 3) Declare '%cpu%::write_stacks' in your cpu class 4) Declare 'int tick' in your cpu class 5) Add 'write_stacks.reset (); tick = 0;' to your %cpu%::reset () method 6) Add the following to %cpu%::step_insns after executing the insn (and catching any exceptions) and before checking for triggerpoints: // Execute writeback try { write_stacks.writeback (tick, this); } catch (cpu_memory_fault& t) { this->memory_trap (t); } catch (cpu_exception& t) { this->yield (); } // move ahead thru circular pipeline tick = (tick + 1) % %cpu%::pipe_sz; > Supposing that those definitions are mergeable, >would it be ok to put back support for the "old" definition in >SID-CGEN? If not, what can be done? > > I think that if both can be supported then that would be "a good thing (tm)". Dave