Re: Again: Disassembly with variable instruction size

[Ronald Hecht <ronald.hecht@uni-rostock.de>]

Hi Dave,

that's it! I had code from m32r in proc.opc. I cleaned up the file and 
it works.

Thanks
Ronald

Dave Brolley wrote:

> This looks like had written code for another port and probably came 
> from the <arch>.opc file you cloned (same location as your .cpu file). 
> You need to edit <arch>.opc to suit the needs of your particular port. 
> If the fr30 disassembly function works for you, then it's probably a 
> good place to start.
>
> I hope this helps,
> Dave
>
> Ronald Hecht wrote:
>
>> Hello,
>>
>> the problem seems to be in <arch>-dis.c. The generated function 
>> my_print_instruction looks wrong. It looks like this*
>>
>> #undef  CGEN_PRINT_INSN
>> #define CGEN_PRINT_INSN my_print_insn
>>
>> static int
>> my_print_insn (CGEN_CPU_DESC cd,
>>           bfd_vma pc,
>>           disassemble_info *info)
>> {
>>  bfd_byte buffer[CGEN_MAX_INSN_SIZE];
>>  bfd_byte *buf = buffer;
>>  int status;
>>  int buflen = (pc & 3) == 0 ? 4 : 2;
>>  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
>>  bfd_byte *x;
>>
>>  /* Read the base part of the insn.  */
>>
>>  status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) 
>> ? 2 : 0),
>>                                      buf, buflen, info);
>>  if (status != 0)
>>    {
>>      (*info->memory_error_func) (status, pc, info);
>>      return -1;
>>    }
>>
>>  /* 32 bit insn?  */
>>  x = (big_p ? &buf[0] : &buf[3]);
>>  if ((pc & 3) == 0 && (*x & 0x80) != 0)
>>    return print_insn (cd, pc, info, buf, buflen);
>>
>>  /* Print the first insn.  */
>>  if ((pc & 3) == 0)
>>    {
>>      buf += (big_p ? 0 : 2);
>>      if (print_insn (cd, pc, info, buf, 2) == 0)
>>    (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
>>      buf += (big_p ? 2 : -2);
>>    }
>>
>>  x = (big_p ? &buf[0] : &buf[1]);
>>  if (*x & 0x80)
>>    {
>>      /* Parallel.  */
>>      (*info->fprintf_func) (info->stream, " || ");
>>      *x &= 0x7f;
>>    }
>>  else
>>    (*info->fprintf_func) (info->stream, " -> ");
>>
>>  /* The "& 3" is to pass a consistent address.
>>     Parallel insns arguably both begin on the word boundary.
>>     Also, branch insns are calculated relative to the word boundary.  */
>>  if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
>>    (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
>>
>>  return (pc & 3) ? 2 : 4;
>> }
>>
>> I replaced it with the stuff from fr30-dis.c :
>>
>> /* Default value for CGEN_PRINT_INSN.
>>   The result is the size of the insn in bytes or zero for an unknown 
>> insn
>>   or -1 if an error occured fetching bytes.  */
>>
>> #ifndef CGEN_PRINT_INSN
>> #define CGEN_PRINT_INSN default_print_insn
>> #endif
>>
>> static int
>> default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info 
>> *info)
>> {
>>  bfd_byte buf[CGEN_MAX_INSN_SIZE];
>>  int buflen;
>>  int status;
>>
>>  /* Attempt to read the base part of the insn.  */
>>  buflen = cd->base_insn_bitsize / 8;
>>  status = (*info->read_memory_func) (pc, buf, buflen, info);
>>
>>  /* Try again with the minimum part, if min < base.  */
>>  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
>>    {
>>      buflen = cd->min_insn_bitsize / 8;
>>      status = (*info->read_memory_func) (pc, buf, buflen, info);
>>    }
>>
>>  if (status != 0)
>>    {
>>      (*info->memory_error_func) (status, pc, info);
>>      return -1;
>>    }
>>
>>  return print_insn (cd, pc, info, buf, buflen);
>> }
>>
>> This works for me. So the bug seems to be in the generation of 
>> <arch>-dis.c
>>
>> Best Regards
>> Ronald
>> *
>
>