From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1865 invoked by alias); 14 Aug 2006 21:19:03 -0000 Received: (qmail 1856 invoked by uid 22791); 14 Aug 2006 21:19:02 -0000 X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 14 Aug 2006 21:18:57 +0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.12.11.20060308/8.12.11) with ESMTP id k7ELItnu002312; Mon, 14 Aug 2006 17:18:55 -0400 Received: from pobox.toronto.redhat.com (pobox.toronto.redhat.com [172.16.14.4]) by int-mx1.corp.redhat.com (8.12.11.20060308/8.12.11) with ESMTP id k7ELIt0R031191; Mon, 14 Aug 2006 17:18:55 -0400 Received: from [172.16.14.227] (IDENT:0vf2SmHoIRO2CWoLw7MWp8PidaPBwIKx@topaz.toronto.redhat.com [172.16.14.227]) by pobox.toronto.redhat.com (8.12.8/8.12.8) with ESMTP id k7ELIt0F032245; Mon, 14 Aug 2006 17:18:55 -0400 Message-ID: <44E0E8BE.5010100@redhat.com> Date: Mon, 14 Aug 2006 21:19:00 -0000 From: Dave Brolley User-Agent: Mozilla Thunderbird 1.0.2 (X11/20050317) MIME-Version: 1.0 To: Ronald Hecht CC: cgen@sourceware.org Subject: Re: Simulator: base_insn and insn in decode.c References: <44CDF0AC.6070707@uni-rostock.de> <44D270CF.30506@redhat.com> <44D273E8.4040006@redhat.com> <44D7549A.7000201@uni-rostock.de> In-Reply-To: <44D7549A.7000201@uni-rostock.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2006-q3/txt/msg00029.txt.bz2 Ronald Hecht wrote: > I switched to the SID framework. I found it easier to create a new > target. The disassemby works better as it calls this disassembler code > in src/opcodes. But I'm still in trouble with decode.cxx. It looks the > same as in sim. I'n my opinion the entire_insn should alwasy be left > aligned and not right_aligned as it is now. Base_insn should have the > same alignment. I think this way it is easier to support variable > sized instructions. > I've been looking at what other ports do and it seems that most are able to pass the same value base_insn and entire_insn because the opcode bits are scattered throughout the insns. The ones which aren't so lucky do one of two things: 1) Write some ugly code which examines the base_insn bits in order to decide how to position entire_insn. 2) Set base-insn-bitsize in the define-isa of the .cpu file to be the size of the largest insn. For SID, base_insn and entire_insn can then be passed identically as the insn bits aligned at the 'base-insn-bitsize' bit. For example, in your case, the max insn length appears to be 24, so you could simply read 3 bytes individually (to avoid endianness problems) and place them sequentially in the low order bytes of base_insn and entire_insn. Barring some redesign of the interface as has been discussed, I don't see any other options for you. Dave