From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11290 invoked by alias); 22 Jan 2009 17:33:37 -0000 Received: (qmail 11273 invoked by uid 22791); 22 Jan 2009 17:33:34 -0000 X-SWARE-Spam-Status: No, hits=-0.9 required=5.0 tests=AWL,BAYES_50,KAM_MX,SPF_HELO_PASS,SPF_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 22 Jan 2009 17:33:29 +0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n0MHXRuN002606 for ; Thu, 22 Jan 2009 12:33:27 -0500 Received: from ns3.rdu.redhat.com (ns3.rdu.redhat.com [10.11.255.199]) by int-mx1.corp.redhat.com (8.13.1/8.13.1) with ESMTP id n0MHXS54016486 for ; Thu, 22 Jan 2009 12:33:28 -0500 Received: from dhcp-10-15-16-104.yyz.redhat.com (dhcp-10-15-16-111.yyz.redhat.com [10.15.16.111]) by ns3.rdu.redhat.com (8.13.8/8.13.8) with ESMTP id n0MHXQS0027077; Thu, 22 Jan 2009 12:33:27 -0500 Message-ID: <4978ADE5.3060700@redhat.com> Date: Thu, 22 Jan 2009 17:33:00 -0000 From: Dave Brolley User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: John Stubley CC: cgen@sources.redhat.com Subject: Re: How does CGEN decide what ifields to use for CGEN_IVALUE? References: <496E30B4.7020400@redhat.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2009-q1/txt/msg00007.txt.bz2 HI John, Sorry to take so long to look at this.... The first potential problem I see is in the use of decode-assist. The bits specified here must be opcode bits for *every* insn. By using decide-assist, this is what you are telling the decoder and it will believe you. According to you, bits 2-0 are not always opcode bits. decode-assist is simply an optimization and I would recommend not using it at all unless the default generated decoder ends up being particularly inefficient. I didn't see any glaring problems otherwise. I hope this helps, Dave John Stubley wrote: > Hi Dave, > > Thank you for your reply. You asked for a few more details, so here > goes: > > The CPU has 16-bit word and 32-bit instruction lengths. The > instructions are mostly packed into bits 3-0 and 31-18, where lsb-0 is > true. The significant bitfields are as follows: > > Opcode family: 4-3 > Opcode (for most instructions): 2-0 > Subopcodes are opcode dependent. > > The problem is that some instructions load immediate data in bits > 2-0,31-18 and thus do not have an opcode field - only an opcode family. > I think what happens is that the immediate data is being used as a hash > in the CGEN_IVALUE part of the table, and so is dependent on the actual > data field. Thus sometimes the disassembler cannot identify the > instruction. > > Below are some extracts from the CPU file (some of the comments need > updating, though). The last instruction shown is the one that will > disassemble oddly: > -----------------------------8<----------------------------------------- > ---- > (define-arch > (name proc16) > (comment "Proc16") > (insn-lsb0? #t) > (machs proc16) > (isas proc16) > ) > > (define-isa > ; Name of the ISA. > (name proc16) > > ; Words size is 16 bits. > (default-insn-word-bitsize 16) > > ; Default instrction length. The insns are always 18 bits wide. > (default-insn-bitsize 32) > > ; Base instruction length. The insns are always 18 bits wide. > (base-insn-bitsize 32) > > ; This may not be needed... > (decode-assist (4 3 2 1 0)) > > ; Fetches 1 insn at a time. > (liw-insns 1) > (parallel-insns 1) > ) > > ; CPU family definitions. > > (define-cpu > ; CPU names must be distinct from the architecture name and machine > names. > ; The "b" suffix stands for "base" and is the convention. > ; The "f" suffix stands for "family" and is the convention. > (name proc16bf) > (comment "Proc16 base family") > (endian little) > (insn-chunk-bitsize 32) > (word-bitsize 16) > ) > > -----------------------------8<----------------------------------------- > ----; Instruction classes. > (dnf f-padhead "unused header" (RESERVED) 15 11) > (dnf f-opfamily "opcode family" () 4 2) > (dnf f-padfoot "unused footer" (RESERVED) 17 2) > (dnf f-opcode "opcode" () 2 3) > (dnf f-padbit "unused bit" (RESERVED) 31 1) > > ; Immediates. > (dnf f-n4 "address offset (4)" () 29 4) > (dnf f-a8 "address (8)" (ABS-ADDR) 29 8) > (dnf f-k7 "imm data (7)" () 28 7) > > (dnf f-a16hi "abs address (16) [15]" () 0 1) > (dnf f-a16lo "abs address (16) [14:0]" () 30 15) > (dnf f-k8hi "imm data (8) [7]" () 30 1) > (dnf f-k8lo "imm data (8) [0-6]" () 28 7) > (dnf f-k16hi "imm data (16) [15:13]" () 2 3) > (dnf f-k16lo "imm data (16) [12:0]" () 30 13) > > (df f-a14 "rel address (14)" (PCREL-ADDR) 29 14 > INT > ((value pc) (sub WI value pc)) > ((value pc) (add WI value pc)) > ) > (dnmf f-a16 "abs address (16)" (ABS-ADDR) > UINT > (f-a16hi f-a16lo) > ; insert > (sequence () > (set (ifield f-a16hi) (srl (ifield f-a16) (const > 15))) > (set (ifield f-a16lo) (and (ifield f-a16) (const > #x7fff))) > ) > ; extract > (sequence () > (set (ifield f-a16) (or (sll (ifield f-a16hi) (const > 15)) > (ifield f-a16lo))) > ) > ) > > > (dnmf f-k8 "imm data (8)" () > UINT > (f-k8hi f-k8lo) > ; insert > (sequence () > (set (ifield f-k8hi) (srl (ifield f-k8) (const 7))) > (set (ifield f-k8lo) (and (ifield f-k8) (const > #x7f))) > ) > ; extract > (sequence () > (set (ifield f-k8) (or (sll (ifield f-k8hi) (const > 7)) > (ifield f-k8lo))) > ) > ) > > (dnmf f-k16 "imm data (16)" () > UINT > (f-k16hi f-k16lo) > ; insert > (sequence () > (set (ifield f-k16hi) (srl (ifield f-k16) (const > 13))) > (set (ifield f-k16lo) (and (ifield f-k16) (const > #x1fff))) > ) > ; extract > (sequence () > (set (ifield f-k16) (or (sll (ifield f-k16hi) (const > 13)) > (ifield f-k16lo))) > ) > ) > -----------------------------8<----------------------------------------- > ----; insn-opfamily: bits 2-3 > (define-normal-insn-enum insn-opfamily "insn family enums" () OPF_ > f-opfamily > (("LOADSTORE" 0) > ("ARITH" 1) > ("BRANCH" 2) > ("SPECIAL" 3)) > ) > > ; insn-opcode-loadstore: bits 31,0-1, Load/Store family > (define-normal-insn-enum insn-opcode-loadstore "l/s insn code enums" () > OPL_ f-opcode > (("LOAD" 0) > ("Reserved1" 1) > ("FETCH" 2) > ("INPUT" 3) > ("STORE" 4) > ("OUTPUT" 5) > ("LOADPC" 6) > ("RET" 7)) > ) > > ; insn-opcode-arithmetic: bits 31,0-1, Arithmetic family > (define-normal-insn-enum insn-opcode-arithmetic "arith insn code enums" > () OPA_ f-opcode > (("ADD" 0) > ("ADC" 1) > ("SUB" 2) > ("SBC" 3) > ("AND" 4) > ("OR" 5) > ("XOR" 6) > ("BIT" 7)) > ) > > -----------------------------8<----------------------------------------- > ---- > ; Instruction operands. > > (dnop k16 "16 bit unsigned immediate" () h-uint f-k16) > (dnop k8 "8 bit unsigned immediate" () h-uint f-k8) > (dnop k7 "7 bit unsigned immediate" () h-uint f-k7) > (dnop a16 "16 bit absolute address" () h-iaddr f-a16) > (dnop a14 "14 bit relative address" () h-iaddr f-a14) > (dnop a8 "8 bit absolute address" () h-addr f-a8) > (dnop n4 "4 bit address offset" () h-addr f-n4) > > (dnop rX "destination register" () h-gr f-rx) > (dnop rY "source register" () h-gr f-ry) > > -----------------------------8<----------------------------------------- > ----; Load / Store instructions > > (dni loadreg "load registers" > () > "load $rX,$rY" > (+ OPF_LOADSTORE OPL_LOAD (f-padhead 0) (f-padbit 0) (f-padfoot 0) > (f-pad5 0) rY rX) > (set rX rY) > () > ) > > (dni loadimm "load immediate" > () > "load $rX,$k8" > (+ OPF_LOADSTORE OPL_LOAD OPAI_IMM (f-padhead 0) (f-padbit 0) > (f-padfoot 0) k8 rX) > (set rX k8) > () > ) > > -----------------------------8<----------------------------------------- > ----; Special instructions > (dni loadword "load word immediate" > () > "load r0,$k16" > (+ OPF_SPECIAL (f-padhead 0) (f-padbit 0) (f-padfoot 0) k16) > (set (reg WI r0) k16) > () > ) > > -----------------------------8<----------------------------------------- > ---- > > John >