From: Dave Brolley <brolley@redhat.com>
To: DJ Delorie <dj@redhat.com>
Cc: cgen@sourceware.org
Subject: Re: [mep] configuration regen
Date: Tue, 03 Feb 2009 16:08:00 -0000 [thread overview]
Message-ID: <49886BEC.4080707@redhat.com> (raw)
In-Reply-To: <200902030217.n132HOXL023662@greed.delorie.com>
Hi DJ,
This looks like the results of running MeP-Integrator on a new default
config file. Correct? Are there any hand-written changes here that you
can highlight for me? Otherwise, it looks ok to me.
Dave
DJ Delorie wrote:
> Toshiba has requested a new default configuration. This is a regen of
> affected files. Ok to apply?
>
> Index: cgen/ChangeLog
> ===================================================================
> RCS file: /cvs/src/src/cgen/ChangeLog,v
> retrieving revision 1.254
> diff -p -U3 -r1.254 cgen/ChangeLog
> --- cgen/ChangeLog 23 Dec 2008 17:31:59 -0000 1.254
> +++ cgen/ChangeLog 3 Feb 2009 01:53:46 -0000
> @@ -1,3 +1,9 @@
> +2009-02-02 DJ Delorie <dj@redhat.com>
> +
> + * cpu/mep-core.cpu: Update to new MeP configuration.
> + * cpu/mep-ext-cop.cpu: Likewise.
> + * cpu/mep.opc: Likewise.
> +
> 2008-12-23 Frank Ch. Eigler <fche@redhat.com>
>
> * sim.scm (-op-gen-queued-write): Add needed symbol->string.
> Index: cgen/cpu/mep-core.cpu
> ===================================================================
> RCS file: /cvs/src/src/cgen/cpu/mep-core.cpu,v
> retrieving revision 1.2
> diff -p -U3 -r1.2 cgen/cpu/mep-core.cpu
> --- cgen/cpu/mep-core.cpu 21 Sep 2007 18:57:39 -0000 1.2
> +++ cgen/cpu/mep-core.cpu 3 Feb 2009 01:53:47 -0000
> @@ -9,7 +9,6 @@
> (isas mep
> ; begin-isa-enum
> ext_core1
> - ext_core2 ext_cop2_16 ext_cop2_32 ext_cop2_48 ext_cop2_64
> ; end-isa-enum
> )
> )
> @@ -39,51 +38,11 @@
> (base-insn-bitsize 32)
> )
>
> -(define-isa
> - (name ext_core2)
> - (comment "MeP core extension instruction set")
> - (default-insn-word-bitsize 32)
> - (default-insn-bitsize 32)
> - (base-insn-bitsize 32)
> -)
> -
> -(define-isa
> - (name ext_cop2_16)
> - (comment "MeP coprocessor instruction set")
> - (default-insn-word-bitsize 32)
> - (default-insn-bitsize 32)
> - (base-insn-bitsize 32)
> -)
> -
> -(define-isa
> - (name ext_cop2_32)
> - (comment "MeP coprocessor instruction set")
> - (default-insn-word-bitsize 32)
> - (default-insn-bitsize 32)
> - (base-insn-bitsize 32)
> -)
> -
> -(define-isa
> - (name ext_cop2_48)
> - (comment "MeP coprocessor instruction set")
> - (default-insn-word-bitsize 32)
> - (default-insn-bitsize 32)
> - (base-insn-bitsize 32)
> -)
> -
> -(define-isa
> - (name ext_cop2_64)
> - (comment "MeP coprocessor instruction set")
> - (default-insn-word-bitsize 32)
> - (default-insn-bitsize 32)
> - (base-insn-bitsize 32)
> -)
> -
> -(define-pmacro all-mep-isas () (ISA mep,ext_core1,ext_core2,ext_cop2_16,ext_cop2_32,ext_cop2_48,ext_cop2_64))
> +(define-pmacro all-mep-isas () (ISA mep,ext_core1))
>
> -(define-pmacro all-mep-core-isas () (ISA mep,ext_core1,ext_core2))
> +(define-pmacro all-mep-core-isas () (ISA mep,ext_core1))
>
> -(define-pmacro all-core-isa-list () mep,ext_core1,ext_core2)
> +(define-pmacro all-core-isa-list () mep,ext_core1)
> ; end-isas
>
> (define-cpu
> @@ -245,6 +204,7 @@
> (psw 16) (id 17) (tmp 18) (epc 19) (exc 20) (cfg 21)
> (npc 23) (dbg 24) (depc 25) (opt 26) (rcfg 27) (ccfg 28)
> ; begin-extra-csr-registers
> + (vid 22)
> ; end-extra-csr-registers
> ))
> (get (index) (c-call SI "cgen_get_csr_value" index))
> @@ -893,8 +853,7 @@
> (for insn)
> (name CONFIG)
> (values NONE ; config-attr-start
> - simple
> - fmax
> + default
> ) ; config-attr-end
> )
>
> Index: cgen/cpu/mep-ext-cop.cpu
> ===================================================================
> RCS file: /cvs/src/src/cgen/cpu/mep-ext-cop.cpu,v
> retrieving revision 1.1
> diff -p -U3 -r1.1 cgen/cpu/mep-ext-cop.cpu
> --- cgen/cpu/mep-ext-cop.cpu 5 Feb 2007 19:46:38 -0000 1.1
> +++ cgen/cpu/mep-ext-cop.cpu 3 Feb 2009 01:53:47 -0000
> @@ -4,5 +4,4 @@
> ; See file COPYING.CGEN for details.
>
> ;; begin-user-isa-includes
> -(include "mep-fmax.cpu")
> ;; end-user-isa-includes
> Index: cgen/cpu/mep.opc
> ===================================================================
> RCS file: /cvs/src/src/cgen/cpu/mep.opc,v
> retrieving revision 1.1
> diff -p -U3 -r1.1 cgen/cpu/mep.opc
> --- cgen/cpu/mep.opc 5 Feb 2007 19:46:38 -0000 1.1
> +++ cgen/cpu/mep.opc 3 Feb 2009 01:53:47 -0000
> @@ -106,22 +106,6 @@ parse_csrn (CGEN_CPU_DESC cd, const char
> }
>
> /* begin-cop-ip-parse-handlers */
> -static const char *
> -parse_fmax_cr (CGEN_CPU_DESC cd,
> - const char **strp,
> - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
> - long *field)
> -{
> - return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_fmax, field);
> -}
> -static const char *
> -parse_fmax_ccr (CGEN_CPU_DESC cd,
> - const char **strp,
> - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
> - long *field)
> -{
> - return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_fmax, field);
> -}
> /* end-cop-ip-parse-handlers */
>
> const char *
> @@ -764,24 +748,6 @@ print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_
> }
>
> /* begin-cop-ip-print-handlers */
> -static void
> -print_fmax_cr (CGEN_CPU_DESC cd,
> - void *dis_info,
> - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
> - long value,
> - unsigned int attrs)
> -{
> - print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_fmax, value, attrs);
> -}
> -static void
> -print_fmax_ccr (CGEN_CPU_DESC cd,
> - void *dis_info,
> - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
> - long value,
> - unsigned int attrs)
> -{
> - print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_fmax, value, attrs);
> -}
> /* end-cop-ip-print-handlers */
>
> /************************************************************\
> @@ -1172,7 +1138,6 @@ init_mep_all_core_isas_mask (void)
> cgen_bitset_set (& mep_all_core_isas_mask, ISA_MEP);
> /* begin-all-core-isas */
> cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE1);
> - cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE2);
> /* end-all-core-isas */
> }
>
> @@ -1185,10 +1150,6 @@ init_mep_all_cop_isas_mask (void)
> return;
> cgen_bitset_init (& mep_all_cop_isas_mask, ISA_MAX);
> /* begin-all-cop-isas */
> - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_16);
> - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_32);
> - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_48);
> - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_64);
> /* end-all-cop-isas */
> }
>
> @@ -1220,12 +1181,9 @@ mep_config_map_struct mep_config_map[] =
> {
> /* config-map-start */
> /* Default entry: mep core only, all options enabled. */
> - { "", 0, EF_MEP_CPU_C2, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
> - { "simple", CONFIG_SIMPLE, EF_MEP_CPU_C2, 1, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
> - 0 },
> - { "fmax", CONFIG_FMAX, EF_MEP_CPU_C2, 1, 0, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x2" }, { 1, "\x1e" }, { 1, "\xa0" },
> + { "", 0, EF_MEP_CPU_C4, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
> + { "default", CONFIG_DEFAULT, EF_MEP_CPU_C4, 0, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
> 0
> - | (1 << CGEN_INSN_OPTIONAL_CP_INSN)
> | (1 << CGEN_INSN_OPTIONAL_MUL_INSN)
> | (1 << CGEN_INSN_OPTIONAL_DIV_INSN)
> | (1 << CGEN_INSN_OPTIONAL_BIT_INSN)
>
next prev parent reply other threads:[~2009-02-03 16:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-02-03 2:17 DJ Delorie
2009-02-03 16:08 ` Dave Brolley [this message]
2009-02-03 17:21 ` DJ Delorie
2009-02-03 19:01 ` Dave Brolley
2009-02-03 21:30 ` DJ Delorie
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