From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20641 invoked by alias); 21 Jun 2009 19:02:41 -0000 Received: (qmail 20463 invoked by uid 22791); 21 Jun 2009 19:02:40 -0000 X-SWARE-Spam-Status: No, hits=-2.1 required=5.0 tests=AWL,BAYES_00,J_CHICKENPOX_43,SPF_PASS X-Spam-Check-By: sourceware.org Received: from ey-out-1920.google.com (HELO ey-out-1920.google.com) (74.125.78.148) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 21 Jun 2009 19:02:32 +0000 Received: by ey-out-1920.google.com with SMTP id 3so330192eyh.26 for ; Sun, 21 Jun 2009 12:02:29 -0700 (PDT) Received: by 10.210.57.3 with SMTP id f3mr3734109eba.60.1245610949364; Sun, 21 Jun 2009 12:02:29 -0700 (PDT) Received: from ?192.168.2.99? (cpc2-cmbg8-0-0-cust61.cmbg.cable.ntl.com [82.6.108.62]) by mx.google.com with ESMTPS id 28sm154702eyg.54.2009.06.21.12.02.28 (version=SSLv3 cipher=RC4-MD5); Sun, 21 Jun 2009 12:02:29 -0700 (PDT) Message-ID: <4A3E86AA.2080002@gmail.com> Date: Sun, 21 Jun 2009 19:02:00 -0000 From: Dave Korn User-Agent: Thunderbird 2.0.0.17 (Windows/20080914) MIME-Version: 1.0 To: cgen@sources.redhat.com Subject: unable to find precise mode to match cpu word-bitsize 24 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2009-q2/txt/msg00056.txt.bz2 Hello CGEN list, I'm attempting to develop a model of a CPU that has a natural 24-bit wordsize: 24-bit registers, 24-bit ALU, 24-bit data bus... 24-bit everything, and no subword or unaligned accesses - in fact, you could really call them 24-bit bytes, as it's the minimum addressable unit. A naive attempt to just write (define-cpu [ . . . ] (word-bitsize 24) [ . . . ] ) fails with the error message from the title of this post. I've crudely hacked in a couple of three-quarter int modes like this: Index: mode.scm =================================================================== RCS file: /cvs/src/src/cgen/mode.scm,v retrieving revision 1.4 diff -p -u -r1.4 mode.scm --- mode.scm 16 Jul 2003 05:35:47 -0000 1.4 +++ mode.scm 21 Jun 2009 18:45:00 -0000 @@ -499,6 +499,7 @@ Define a mode, all arguments specified. (dfm 'QI "8 bit byte" '() 'INT 8 1 "int" "'x'" #f #f #f) (dfm 'HI "16 bit int" '() 'INT 16 2 "int" "'x'" #f #f #f) + (dfm 'TQI "24 bit int" '() 'INT 24 3 "int" "'x'" #f #f #f) (dfm 'SI "32 bit int" '() 'INT 32 4 "int" "'x'" #f #f #f) (dfm 'DI "64 bit int" '(FN-SUPPORT) 'INT 64 8 "" "'D'" #f #f #f) @@ -506,6 +507,8 @@ Define a mode, all arguments specified. 8 1 "unsigned int" "'x'" (mode:lookup 'QI) #f #f) (dfm 'UHI "16 bit unsigned int" '() 'UINT 16 2 "unsigned int" "'x'" (mode:lookup 'HI) #f #f) + (dfm 'UTQI "24 bit unsigned int" '() 'UINT + 24 3 "unsigned int" "'x'" (mode:lookup 'TQI) #f #f) (dfm 'USI "32 bit unsigned int" '() 'UINT 32 4 "unsigned int" "'x'" (mode:lookup 'SI) #f #f) (dfm 'UDI "64 bit unsigned int" '(FN-SUPPORT) 'UINT just so that I can get on with writing my i-fields, but will it work? If I want my (simulated) pc to increment in steps of 1, not 3, should I define the number of bytes to 1 instead of 3? Or would I be best off redefining QI mode altogether? Sorry if this is a n00b question, but a bit of googling and grepping didn't show up anyone trying this before. cheers, DaveK