From: Dave Korn <dave.korn.cygwin@googlemail.com>
To: Doug Evans <dje@sebabeach.org>
Cc: Dave Korn <dave.korn.cygwin@googlemail.com>, cgen@sources.redhat.com
Subject: Re: unable to find precise mode to match cpu word-bitsize 24
Date: Sat, 04 Jul 2009 23:35:00 -0000 [thread overview]
Message-ID: <4A4FEA13.1090104@gmail.com> (raw)
In-Reply-To: <4A3FB9D5.9070103@sebabeach.org>
Doug Evans wrote:
> Dave Korn wrote:
>> Doug Evans wrote:
>>
>>
>>> This is new ground so we can decide how we want things to look, and then
>>> make it work.
>>>
>>
>> Well, what I'd particularly like in this case would be for my pc to
>> increment by one for each 24-bit insn, rather than have the model
>> pretend to
>> be an 8-bit CISC machine processing all 3-byte instructions, if you
>> see what I
>> mean.
>>
>
> Righto. That should be doable regardless.
I hope so. Should I just take the blunt sledgehammer approach, and define
setters and getters for hardware units h-addr and h-iaddr that multiply/divide
by 3 on the fly, and let the underlying framework pretend it's a CISC machine
that uses 3-byte operands and data? Or is there a cleaner way to go?
cheers,
DaveK
next prev parent reply other threads:[~2009-07-04 23:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-06-21 19:02 Dave Korn
2009-06-21 23:07 ` Doug Evans
2009-06-22 0:05 ` Dave Korn
2009-06-22 17:05 ` Doug Evans
2009-07-04 23:35 ` Dave Korn [this message]
2009-07-14 5:59 ` Doug Evans
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