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Date: Wed, 28 Oct 2009 16:40:00 -0000
From: Doug Evans <dje@sebabeach.org>
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To: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
CC: Dave Korn <dave.korn.cygwin@googlemail.com>,   cgen <cgen@sources.redhat.com>
Subject: Re: cgen->sim question
References: <bc64b4640910260345q1c91fed2r739530081dbb1a6c@mail.gmail.com>	 <4AE59913.5040402@gmail.com> <4AE5CA87.5030500@sebabeach.org> <bc64b4640910261312m5a0203au30a3807dd02fe6e6@mail.gmail.com>
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Dmitry Eremin-Solenikov wrote:
> Hello,
>
> On Mon, Oct 26, 2009 at 7:12 PM, Doug Evans <dje@sebabeach.org> wrote:
>   
>> Dave Korn wrote:
>>     
>>> Dmitry Eremin-Solenikov wrote:
>>>
>>>       
>>>> Hello,
>>>>
>>>> I have a question regarding generating sim code from cgen description.
>>>>
>>>> I have an instruction operand instantiated from field with type h-addr.
>>>> If in the semantics part of the instruction I try to access the operandr
>>>> as an address: '(mem QI ddaddr)', I get an error from cgen:
>>>>
>>>> simplify.inc:131:3: op:new-mode: invalid mode for operand `ddaddr': USI
>>>>
>>>> This is the definition of ddaddr:
>>>>
>>>> (dif f-dd-1 "1-byte direct address at 1 position" (ABS-ADDR) 8 8 0 8 UINT
>>>> #f #f)
>>>> (dno ddaddr "direct address" () h-addr f-dd-1)
>>>>         
>
>   
>> What does the instruction definition look like?
>>     
>
> Please see the attachment. The stamp-cpu (cgen-cpu-decode) fails on
> this CPU file.
>
>   

I checked in this patch.

2009-10-28  Doug Evans  <dje@sebabeach.org>

        * cos.scm (object-assign!): New function.
        * mode.scm (/mode-set-word-params!): Call it.