From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 30389 invoked by alias); 23 Apr 2010 13:44:40 -0000 Received: (qmail 30380 invoked by uid 22791); 23 Apr 2010 13:44:38 -0000 X-SWARE-Spam-Status: No, hits=2.2 required=5.0 tests=BAYES_00,TW_YC,URIBL_BLACK X-Spam-Check-By: sourceware.org Received: from claranetfr-outbound-smtp02.mail.eu.clara.net (HELO claranetfr-outbound-smtp02.mail.eu.clara.net) (195.8.64.51) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 23 Apr 2010 13:44:31 +0000 Received: from 98.140.74-86.rev.gaoland.net ([86.74.140.98]:56301 helo=[192.168.0.100]) by relay02.mail.eu.clara.net (smtp-vh.fr.clara.net [213.253.3.42]:1725) with esmtpa (authdaemon_plain:jean-marc.saffroy@joguin.com) id 1O5JBC-0001kp-7s (return-path ); Fri, 23 Apr 2010 13:44:27 +0000 Message-ID: <4BD1A40D.3040706@joguin.com> Date: Fri, 23 Apr 2010 13:44:00 -0000 From: Jean-Marc Saffroy User-Agent: Thunderbird 2.0.0.24 (X11/20100317) MIME-Version: 1.0 To: Richard Herveille CC: cgen@sources.redhat.com Subject: Re: unresolved symbols during binutils linking References: <4BD07B40.8020405@herveille.net> <4BD19C6F.3000304@joguin.com> In-Reply-To: <4BD19C6F.3000304@joguin.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2010-q2/txt/msg00003.txt.bz2 Hmm it seems there are other places where you need to mention these files. FWIW below is the patch I use. HTH, JM Jean-Marc Saffroy wrote: > Hi Richard, > > Maybe you forgot to add mycpu-{asm,desc,dis,ibld,opc}.c to > TARGET_LIBOPCODES_CFILES in opcodes/Makefile.am (and of course > regenerate Makefile.in and rerun configure) ? > > Cheers, > JM > > Richard Herveille wrote: >> Hi, >> >> I am trying to port binutils to a new CPU using CGEN. >> My approach ... start with a basic/simple .cpu file (with limited >> opcodes) and add instructions once it all starts working. >> >> I think I modified all configure/makefiles in binutils; at least it is >> alive :-) >> I can also see that cgen gets called and generates the files without >> issuing any errors. I can also see the opcode definitions in teh fiels. >> However I am getting errors during compilation (actually during linking); >> >> Example: >> libtool: link: gcc -W ... ../opcodes/.libs/libopcodes.a(mycpu-dis.o): >> In function 'mycpu_cgen_init_dis': >> ... mycpu-dis.c:148 undefined reference to 'mycpu_cgen_init_ibld_table' >> >> other undefined references: >> mycpu_cgen_cpu_open, mycpu_cgen_opval_h_gpr, mycpu_cgen_opval_h_gpar, >> mycpu_cgen_init_opcode_table, mycpu_cgen_build_insn_regex >> >> I can see all of these functions being defined in the generated C >> files. I can also see that the names are present in libopcodes.a. >> >> Does anybody have any clue what is going wrong? I tried other targets >> and they work out of the box. So it must be something in my CPU's setup. >> >> Thanks, >> Richard >> >> >> > > --- a/include/dis-asm.h Mon Mar 22 15:03:12 2010 +0100 +++ b/include/dis-asm.h Mon Mar 22 16:02:04 2010 +0100 @@ -273,6 +273,7 @@ extern int print_insn_msp430 (bfd_vma, disassemble_info *); extern int print_insn_mt (bfd_vma, disassemble_info *); extern int print_insn_ns32k (bfd_vma, disassemble_info *); +extern int print_insn_mycpu (bfd_vma, disassemble_info *); extern int print_insn_openrisc (bfd_vma, disassemble_info *); extern int print_insn_pdp11 (bfd_vma, disassemble_info *); extern int print_insn_pj (bfd_vma, disassemble_info *); --- a/opcodes/Makefile.am Mon Mar 22 15:03:12 2010 +0100 +++ b/opcodes/Makefile.am Mon Mar 22 16:02:04 2010 +0100 @@ -174,6 +174,11 @@ mt-ibld.c \ mt-opc.c \ ns32k-dis.c \ + mycpu-asm.c \ + mycpu-desc.c \ + mycpu-dis.c \ + mycpu-ibld.c \ + mycpu-opc.c \ openrisc-asm.c \ openrisc-desc.c \ openrisc-dis.c \ @@ -305,7 +310,7 @@ && mv tmp $(srcdir)/po/POTFILES.in CLEANFILES = \ - stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ + stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv stamp-mycpu \ stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -322,7 +327,7 @@ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16 +CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt mycpu openrisc xc16x xstormy16 if CGEN_MAINT FR30_DEPS = stamp-fr30 @@ -334,6 +339,7 @@ M32R_DEPS = stamp-m32r MEP_DEPS = stamp-mep MT_DEPS = stamp-mt +MYCPU_DEPS = stamp-mycpu OPENRISC_DEPS = stamp-openrisc XC16X_DEPS = stamp-xc16x XSTORMY16_DEPS = stamp-xstormy16 @@ -347,6 +353,7 @@ M32R_DEPS = MEP_DEPS = MT_DEPS = +MYCPU_DEPS = OPENRISC_DEPS = XC16X_DEPS = XSTORMY16_DEPS = @@ -431,6 +438,12 @@ archfile=$(srcdir)/../cpu/mt.cpu \ opcfile=$(srcdir)/../cpu/mt.opc extrafiles= +$(srcdir)/mycpu-desc.h $(srcdir)/mycpu-desc.c $(srcdir)/mycpu-opc.h $(srcdir)/mycpu-opc.c $(srcdir)/mycpu-ibld.c $(srcdir)/mycpu-asm.c $(srcdir)/mycpu-dis.c: $(MYCPU_DEPS) + @true +stamp-mycpu: $(CGENDEPS) $(srcdir)/../cpu/mycpu.cpu $(srcdir)/../cpu/mycpu.opc + $(MAKE) run-cgen arch=mycpu prefix=mycpu options= \ + archfile=$(srcdir)/../cpu/mycpu.cpu opcfile=$(srcdir)/../cpu/mycpu.opc extrafiles= + $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc --- a/opcodes/configure.in Mon Mar 22 15:03:12 2010 +0100 +++ b/opcodes/configure.in Mon Mar 22 16:02:04 2010 +0100 @@ -262,6 +262,7 @@ bfd_mt_arch) ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;; bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; + bfd_mycpu_arch) ta="$ta mycpu-asm.lo mycpu-desc.lo mycpu-dis.lo mycpu-ibld.lo mycpu-opc.lo" using_cgen=yes ;; bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;; bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;; --- a/opcodes/disassemble.c Mon Mar 22 15:03:12 2010 +0100 +++ b/opcodes/disassemble.c Mon Mar 22 16:02:04 2010 +0100 @@ -65,6 +65,7 @@ #define ARCH_mt #define ARCH_msp430 #define ARCH_ns32k +#define ARCH_mycpu #define ARCH_openrisc #define ARCH_or32 #define ARCH_pdp11 @@ -319,6 +320,11 @@ disassemble = print_insn_openrisc; break; #endif +#ifdef ARCH_mycpu + case bfd_arch_mycpu: + disassemble = print_insn_mycpu; + break; +#endif #ifdef ARCH_or32 case bfd_arch_or32: if (bfd_big_endian (abfd))