From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 500 invoked by alias); 5 Aug 2010 12:36:15 -0000 Received: (qmail 489 invoked by uid 22791); 5 Aug 2010 12:36:14 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=BAYES_00 X-Spam-Check-By: sourceware.org Received: from claranetfr-outbound-smtp03.mail.eu.clara.net (HELO claranetfr-outbound-smtp03.mail.eu.clara.net) (195.8.64.52) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 05 Aug 2010 12:36:08 +0000 Received: from 28.165.100-84.rev.gaoland.net ([84.100.165.28]:49983 helo=[192.168.0.100]) by relay03.mail.eu.clara.net (smtp-vh.fr.clara.net [213.253.3.43]:1725) with esmtpa (authdaemon_plain:jean-marc.saffroy@joguin.com) id 1Ogzg5-00070l-Ad (return-path ); Thu, 05 Aug 2010 12:36:05 +0000 Message-ID: <4C5AB033.5000407@joguin.com> Date: Tue, 24 Aug 2010 04:34:00 -0000 From: Jean-Marc Saffroy User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.11) Gecko/20100713 Thunderbird/3.0.6 MIME-Version: 1.0 To: Petronela Agache CC: cgen@sourceware.org Subject: Re: dni format description References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2010-q3/txt/msg00004.txt.bz2 Hi Petronela, Please post to only one instance of the cgen list, thank you. On 08/05/2010 10:23 AM, Petronela Agache wrote: > Hello, > My name is Petronela, i would like to get more info about the format > field from pmacros. For example the following insn is used in > m32r.cpu: > (dni addx "addx" > > ((PIPE OS) (IDOC ALU)) > "addx $dr,$sr" > (+ OP1_0 OP2_9 dr sr) > (parallel () > (set dr (addc dr sr condbit)) > (set condbit (add-cflag dr sr condbit))) > () > > ) > What (+ OP1_0 OP2_9 dr sr) means ? This is the format for this instruction. It means that this particular instruction has 4 fields, of which 2 (OP1_0 and OP2_9) have a fixed value. It's only the layout of the instruction, ie. which bits are constant (typically the instruction opcode) and which are not (instruction operands). Above the dni macro, you will find definitions for various instruction fields. This instruction is a combination of 4 of those fields, which cover exactly all the bits in the instruction. > OP1_* and OP2_* are defined in the > following way: > (define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1 > > ("0" "1" "2" "3" "4" "5" "6" "7" > "8" "9" "10" "11" "12" "13" "14" "15") > > ) > (define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2 > > ("0" "1" "2" "3" "4" "5" "6" "7" > "8" "9" "10" "11" "12" "13" "14" "15") > > ) Yes, so OP1_0 means field f-op1 of an instruction, with constant value 0 for those bits. Same for OP2_9. On the other hand, dr and sr are defined as fields which are to be interpreted as register numbers. > My understanding is that destination register is always R0 and source > register is always R9 for this type of insn. Is this correct ? Does > this not restrict the hardware usage ? Since this insn can be executed > on all R* registers. This is not correct. The actual semantic of the instruction is after the format: > (parallel () > (set dr (addc dr sr condbit)) > (set condbit (add-cflag dr sr condbit))) > () This describes how instruction operands are used. In this example: - add 3 registers: explicit operands dr and sr, and implicit operand condbit - put the result in register dr - compute the carry for the same addition - put the carry in register condbit Hope this helps. Jean-Marc > > Thank you >