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* Macro with same operands is misbehaving
@ 2019-04-05 14:44 Paulo Matos
  2019-04-08  1:28 ` Frank Ch. Eigler
  0 siblings, 1 reply; 3+ messages in thread
From: Paulo Matos @ 2019-04-05 14:44 UTC (permalink / raw)
  To: cgen

Hi,

Before going ahead and start modifying CGEN I wanted to confirm if one
can implement something like this with the current CGEN.

Take a floating point instruction like the RISC-V `fsgnj.s f0, f1, 2`.
`fmv.s` is a floating point move instruction that can be defined in
terms of `fsgnj.s` as:
`fmv.s f0, f1` == `fsgnj.s f0, f1, f1`.

If I define the instruction fsgnj.s and followed by fmv.s macro, during
disassembly `fsgnj.s` is always chosen, although assembly works fine.
If on the other hand I define `fmv.s` macro followed by the instruction,
assembly works fine again but all disassembly is broken because the
instruction `fsgnj.s ft0, ft1, ft2` will be disassembled as `fmv.s ft0,
ft1` - i.e. ft2 is ignored.

I can't find a way to say: `fmv.s` matches for disassembly but only if
`f1` == `f2` in `fsgnj.s f0, f1, f2`.

I tried to actually define `fmv.s` as a new instruction instead of a
macro but it doesn't work. Actually the same problem occurs because
bitwise `fmv.s` is going to be the same as a `fsgnj.s` with two
registers being the same.

How can I tell the disassembler in CGEN about this `fmv.s` constraint?

-- 
Paulo Matos

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: Macro with same operands is misbehaving
  2019-04-05 14:44 Macro with same operands is misbehaving Paulo Matos
@ 2019-04-08  1:28 ` Frank Ch. Eigler
  2019-04-08  6:09   ` Paulo Matos
  0 siblings, 1 reply; 3+ messages in thread
From: Frank Ch. Eigler @ 2019-04-08  1:28 UTC (permalink / raw)
  To: Paulo Matos; +Cc: cgen

Hi -

> If I define the instruction fsgnj.s and followed by fmv.s macro, during
> disassembly `fsgnj.s` is always chosen, although assembly works fine.
> [...]
> I can't find a way to say: `fmv.s` matches for disassembly but only if
> `f1` == `f2` in `fsgnj.s f0, f1, f2`.

I don't know of a way either, at the cgen .cpu level.  But I must ask
... why is this particular disassembly heuristic seem important, given
that those are equivalent?  Anyway, it may be possible to handle at
the disassmembler driver level (in C code) even if .cpu/cgen can't
express it.

- FChE

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: Macro with same operands is misbehaving
  2019-04-08  1:28 ` Frank Ch. Eigler
@ 2019-04-08  6:09   ` Paulo Matos
  0 siblings, 0 replies; 3+ messages in thread
From: Paulo Matos @ 2019-04-08  6:09 UTC (permalink / raw)
  To: cgen



On 08/04/2019 03:28, Frank Ch. Eigler wrote:
> Hi -
> 
>> If I define the instruction fsgnj.s and followed by fmv.s macro, during
>> disassembly `fsgnj.s` is always chosen, although assembly works fine.
>> [...]
>> I can't find a way to say: `fmv.s` matches for disassembly but only if
>> `f1` == `f2` in `fsgnj.s f0, f1, f2`.
> 
> I don't know of a way either, at the cgen .cpu level.  But I must ask
> ... why is this particular disassembly heuristic seem important, given
> that those are equivalent?  Anyway, it may be possible to handle at
> the disassmembler driver level (in C code) even if .cpu/cgen can't
> express it.
> 

The client reckons it's important to show the macro version when
possible. :)

When you mean at the disassembler level in C, I then assume there's a
hook that cgen calls before printing a disassembly string to the output
that I can use to mangle the string back into the macro version?

-- 
Paulo Matos

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2019-04-08  6:09 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2019-04-05 14:44 Macro with same operands is misbehaving Paulo Matos
2019-04-08  1:28 ` Frank Ch. Eigler
2019-04-08  6:09   ` Paulo Matos

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