From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from userp2130.oracle.com (userp2130.oracle.com [156.151.31.86]) by sourceware.org (Postfix) with ESMTPS id C468E3897826 for ; Tue, 19 May 2020 12:47:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org C468E3897826 Received: from pps.filterd (userp2130.oracle.com [127.0.0.1]) by userp2130.oracle.com (8.16.0.42/8.16.0.42) with SMTP id 04JCl7qR186768 for ; Tue, 19 May 2020 12:47:35 GMT Received: from aserp3030.oracle.com (aserp3030.oracle.com [141.146.126.71]) by userp2130.oracle.com with ESMTP id 3127kr553h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Tue, 19 May 2020 12:47:35 +0000 Received: from pps.filterd (aserp3030.oracle.com [127.0.0.1]) by aserp3030.oracle.com (8.16.0.42/8.16.0.42) with SMTP id 04JCcll2195597 for ; Tue, 19 May 2020 12:47:35 GMT Received: from userv0121.oracle.com (userv0121.oracle.com [156.151.31.72]) by aserp3030.oracle.com with ESMTP id 313gj1maym-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 19 May 2020 12:47:34 +0000 Received: from abhmp0010.oracle.com (abhmp0010.oracle.com [141.146.116.16]) by userv0121.oracle.com (8.14.4/8.13.8) with ESMTP id 04JClXjU001076 for ; Tue, 19 May 2020 12:47:34 GMT Received: from termi.oracle.com (/10.175.36.22) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Tue, 19 May 2020 05:47:33 -0700 From: "Jose E. Marchesi" To: cgen@sourceware.org Subject: [PATCH] desc-cpu.scm: support passing the instruction endianness to cgen_cpu_open Date: Tue, 19 May 2020 14:45:41 +0200 Message-ID: <87mu64jdoq.fsf@oracle.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.0.50 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9625 signatures=668686 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 spamscore=0 malwarescore=0 mlxscore=0 adultscore=0 bulkscore=0 suspectscore=1 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2005190113 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9625 signatures=668686 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 spamscore=0 bulkscore=0 clxscore=1011 priorityscore=1501 mlxscore=0 impostorscore=0 suspectscore=1 mlxlogscore=999 malwarescore=0 cotscore=-2147483648 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2005190114 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: cgen@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Cgen mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 May 2020 12:47:38 -0000 Hi people! This patch adds support for specifying the "instruction endianness" (as oppossed to data endianness) when calling cgen_cpu_open. This is part of a bigger work to properly support arches like BPF, where the endianness of the instruction is different to the endianness of the contents of the instruction's fields. The accompanying patch for opcodes will be sent to binutils@sourceware.org today. This CGEN patch will have to be applied first though. OK for master? 2020-05-19 Jose E. Marchesi * desc-cpu.scm (/gen-cpu-open): Support passing the instruction endianness to cgen_cpu_open. diff --git a/desc-cpu.scm b/desc-cpu.scm index b24c9f2..e00d8cd 100644 --- a/desc-cpu.scm +++ b/desc-cpu.scm @@ -788,6 +788,7 @@ static void CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice CGEN_CPU_OPEN_END: terminates arguments ??? Simultaneous multiple isas might not make sense, but it's not (yet) @@ -801,6 +802,7 @@ CGEN_CPU_DESC CGEN_BITSET *isas = 0; /* 0 = \"unspecified\" */ unsigned int machs = 0; /* 0 = \"unspecified\" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN; va_list ap; if (! init_p) @@ -835,6 +837,9 @@ CGEN_CPU_DESC case CGEN_CPU_OPEN_ENDIAN : endian = va_arg (ap, enum cgen_endian); break; + case CGEN_CPU_OPEN_INSN_ENDIAN : + insn_endian = va_arg (ap, enum cgen_endian); + break; default : opcodes_error_handler (/* xgettext:c-format */ @@ -864,11 +869,8 @@ CGEN_CPU_DESC cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; - /* FIXME: for the sparc case we can determine insn-endianness statically. - The worry here is where both data and insn endian can be independently - chosen, in which case this function will need another argument. - Actually, will want to allow for more arguments in the future anyway. */ - cd->insn_endian = endian; + if (insn_endian == CGEN_ENDIAN_UNKNOWN) + cd->insn_endian = endian; /* Table (re)builder. */ cd->rebuild_tables = @arch@_cgen_rebuild_tables;