From: "Jose E. Marchesi" <jose.marchesi@oracle.com>
To: "Frank Ch. Eigler via Cgen" <cgen@sourceware.org>
Cc: Sergey Belyashov <sergey.belyashov@gmail.com>,
"Frank Ch. Eigler" <fche@redhat.com>
Subject: Re: BUG: non-fixed-length ISAs are unsupported for now
Date: Wed, 12 Aug 2020 20:53:42 +0200 [thread overview]
Message-ID: <87pn7v1yrt.fsf@oracle.com> (raw)
In-Reply-To: <20200812183611.GA27698@redhat.com> (Frank Ch. Eigler via Cgen's message of "Wed, 12 Aug 2020 14:36:11 -0400")
>> I have tried it. Result is the same: ifields are just added (part of
>> generated z80-opc.c):
>
> I'm unfortunately unable to actually run cgen here (apparent
> incompatibility with "new" fedora32-level guile), so am only guessing
> that you could try setting the cpu base-insn-size to 16 or even 32:
> enough bits to tell the instructions apart.
That looks like the right approach.
Currently CGEN does not support having opcodes (constant fields) past
the base part of the insn, which by the way is limited to a maximum of
32-bit.
next prev parent reply other threads:[~2020-08-12 18:53 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-23 13:37 Sergey Belyashov
2020-04-27 16:29 ` Frank Ch. Eigler
2020-04-27 17:00 ` Sergey Belyashov
2020-04-27 17:52 ` Sergey Belyashov
2020-04-27 18:03 ` Jose E. Marchesi
2020-04-27 19:34 ` Sergey Belyashov
2020-04-27 20:01 ` Jose E. Marchesi
2020-04-27 20:23 ` Sergey Belyashov
2020-04-29 19:11 ` Sergey Belyashov
2020-07-30 9:11 ` Sergey Belyashov
2020-08-11 15:38 ` Frank Ch. Eigler
2020-08-11 15:57 ` Sergey Belyashov
2020-08-11 16:08 ` Frank Ch. Eigler
2020-08-12 13:59 ` Sergey Belyashov
2020-08-12 18:36 ` Frank Ch. Eigler
2020-08-12 18:53 ` Jose E. Marchesi [this message]
2020-08-12 19:19 ` Sergey Belyashov
2020-08-12 19:21 ` Frank Ch. Eigler
2020-08-12 19:27 ` Jose E. Marchesi
2020-08-12 19:44 ` Sergey Belyashov
2020-08-12 19:57 ` Frank Ch. Eigler
2020-08-13 13:34 ` Sergey Belyashov
2020-08-13 14:32 ` Frank Ch. Eigler
2020-08-13 14:47 ` Sergey Belyashov
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