Hi there

Hi there

[Jose E. Marchesi]

Hi.

Just wanted to say hello, since I just got subscribed :)

I am using cgen for the development of a LEON3 simulator, partly funded
by my employer.

-- 
Jose E. Marchesi         http://www.jemarch.net
GNU Project              http://www.gnu.org

Re: Hi there

[Frank Ch. Eigler]

Hi, Jose -

> I am using cgen for the development of a LEON3 simulator, partly funded
> by my employer.

Neat.  Are you starting from one of the other SPARC models?  Which
simulator framework are you planning to use (gdb/sim vs. sid)?

- FChE

Re: Hi there

[Jose E. Marchesi]

    > I am using cgen for the development of a LEON3 simulator, partly funded
    > by my employer.
    
    Neat.  Are you starting from one of the other SPARC models?

Probably yes.  I am currently reading the cgen/cpu/sparc*.cpu RTL files.
It looks like they are not being updated since long ago, and that they
are not being used in binutils.

I copied them into my local git repo (which will be public as soon as I
reach a stage where at least the ISA simulator runs) since I need to do
extensive modifications, such as explicitly supporting a V7 machine for
ERC32 and the models themselves.

    Which simulator framework are you planning to use (gdb/sim vs. sid)?

gdb.  I am still in the stage on getting familiar with the common sim
infrastructure, but it looks like it provides enough flexibility (in
terms of buses, signals, etc) for my purposes.

Besides, my company filed a copyright assignment for gdb, and I have got
a personal one in place as well :)

BTW, do I need to sign separated papers for CGEN?

-- 
Jose E. Marchesi         http://www.jemarch.net
GNU Project              http://www.gnu.org

Re: Hi there

[Frank Ch. Eigler]

Hi -

On Thu, Jan 19, 2012 at 10:01:15PM +0100, Jose E. Marchesi wrote:
> [...]
>     Which simulator framework are you planning to use (gdb/sim vs. sid)?
> 
> gdb.  I am still in the stage on getting familiar with the common sim
> infrastructure, but it looks like it provides enough flexibility (in
> terms of buses, signals, etc) for my purposes.

OK.  sid's flexibility may become needed if you want to model more
peculiar hardware, like different cpus, unusual peripherals, but you'll
know when/if you get there.

> Besides, my company filed a copyright assignment for gdb, and I have got
> a personal one in place as well :)

OK.

> BTW, do I need to sign separated papers for CGEN?

What you have should be fine.  We have lots of (C)FSF .cpu files in
the /src/cpu repo.

- FChE

Re: Hi there

[Jose E. Marchesi]

    > BTW, do I need to sign separated papers for CGEN?
    
    What you have should be fine.  We have lots of (C)FSF .cpu files in
    the /src/cpu repo.

Great :) Would you welcome fixes/improvements in the sparc cpu files?  I
am targetting sparc v7, sparc v8 and sparcv8e plus some additions, but I
would be happy improving the sparc 64 machs as well.

-- 
Jose E. Marchesi         http://www.jemarch.net
GNU Project              http://www.gnu.org