From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id E91E43851C2C for ; Fri, 29 May 2020 14:52:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org E91E43851C2C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=gnu.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=jemarch@gnu.org Received: from fencepost.gnu.org ([2001:470:142:3::e]:40377) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jegMl-0000JS-2a; Fri, 29 May 2020 10:52:11 -0400 Received: from [141.143.193.79] (port=20747 helo=termi.gnu.org) by fencepost.gnu.org with esmtpsa (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.82) (envelope-from ) id 1jegMk-0007Gh-Iw; Fri, 29 May 2020 10:52:10 -0400 From: "Jose E. Marchesi" To: "Frank Ch. Eigler via Cgen" Cc: "Jose E. Marchesi" Subject: Re: [PATCH] desc-cpu.scm: support passing the instruction endianness to cgen_cpu_open References: <87mu64jdoq.fsf@oracle.com> <20200521012617.GD21615@redhat.com> <87zha1lnpw.fsf@gnu.org> Date: Fri, 29 May 2020 16:52:04 +0200 In-Reply-To: <87zha1lnpw.fsf@gnu.org> (Jose E. Marchesi's message of "Thu, 21 May 2020 10:02:51 +0200") Message-ID: <87v9kekd4b.fsf@gnu.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.0.50 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: cgen@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Cgen mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 May 2020 14:52:14 -0000 > The accompanying patch for opcodes will be sent to > binutils@sourceware.org today. This CGEN patch will have to be applied > first though. > > OK for master? Sure, and it seems to have been anticipated. Thanks. I will push once the binutils stuff is also ready... found a complication. Ok I think I got the binutils side nailed. Will post the patches to binutils@sourceware once regression testing finishes running, later today. After the binutils part is approved I will push the following (fixed) version of the CGEN patch, to master: commit b684299385722879c5658f99cdbe0c63a8bc7362 (HEAD -> jemarch/cgen-insn-endian, malditobastardo/jemarch/cgen-insn-endian) Author: Jose E. Marchesi Date: Fri May 29 16:03:48 2020 +0200 desc-cpu.scm: support passing the instruction endianness to cgen_cpu_open 2020-05-29 Jose E. Marchesi * desc-cpu.scm (/gen-cpu-open): Support passing the instruction endianness to cgen_cpu_open. diff --git a/ChangeLog b/ChangeLog index e554fa2..93eafe4 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2020-05-29 Jose E. Marchesi + + * desc-cpu.scm (/gen-cpu-open): Support passing the instruction + endianness to cgen_cpu_open. + 2020-05-21 Alan Modra * desc-cpu.scm (@arch@_cgen_cpu_close): Free without first diff --git a/desc-cpu.scm b/desc-cpu.scm index 5bf5bc7..34f5d5c 100644 --- a/desc-cpu.scm +++ b/desc-cpu.scm @@ -788,6 +788,7 @@ static void CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice CGEN_CPU_OPEN_END: terminates arguments ??? Simultaneous multiple isas might not make sense, but it's not (yet) @@ -801,6 +802,7 @@ CGEN_CPU_DESC CGEN_BITSET *isas = 0; /* 0 = \"unspecified\" */ unsigned int machs = 0; /* 0 = \"unspecified\" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN; va_list ap; if (! init_p) @@ -835,6 +837,9 @@ CGEN_CPU_DESC case CGEN_CPU_OPEN_ENDIAN : endian = va_arg (ap, enum cgen_endian); break; + case CGEN_CPU_OPEN_INSN_ENDIAN : + insn_endian = va_arg (ap, enum cgen_endian); + break; default : opcodes_error_handler (/* xgettext:c-format */ @@ -864,11 +869,8 @@ CGEN_CPU_DESC cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; - /* FIXME: for the sparc case we can determine insn-endianness statically. - The worry here is where both data and insn endian can be independently - chosen, in which case this function will need another argument. - Actually, will want to allow for more arguments in the future anyway. */ - cd->insn_endian = endian; + cd->insn_endian + = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian); /* Table (re)builder. */ cd->rebuild_tables = @arch@_cgen_rebuild_tables;