From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12136 invoked by alias); 26 Feb 2012 14:49:36 -0000 Received: (qmail 12123 invoked by uid 22791); 26 Feb 2012 14:49:35 -0000 X-SWARE-Spam-Status: No, hits=-1.0 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-yw0-f41.google.com (HELO mail-yw0-f41.google.com) (209.85.213.41) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 26 Feb 2012 14:49:18 +0000 Received: by yhoo22 with SMTP id o22so2037568yho.0 for ; Sun, 26 Feb 2012 06:49:18 -0800 (PST) Received-SPF: pass (google.com: domain of lyudalev@gmail.com designates 10.236.184.202 as permitted sender) client-ip=10.236.184.202; Authentication-Results: mr.google.com; spf=pass (google.com: domain of lyudalev@gmail.com designates 10.236.184.202 as permitted sender) smtp.mail=lyudalev@gmail.com; dkim=pass header.i=lyudalev@gmail.com Received: from mr.google.com ([10.236.184.202]) by 10.236.184.202 with SMTP id s50mr15804048yhm.86.1330267758454 (num_hops = 1); Sun, 26 Feb 2012 06:49:18 -0800 (PST) MIME-Version: 1.0 Received: by 10.236.184.202 with SMTP id s50mr11766262yhm.86.1330267758424; Sun, 26 Feb 2012 06:49:18 -0800 (PST) Received: by 10.236.116.104 with HTTP; Sun, 26 Feb 2012 06:49:18 -0800 (PST) In-Reply-To: References: Date: Sun, 26 Feb 2012 14:49:00 -0000 Message-ID: Subject: Unusual architecture support? From: Lev Yudalevich To: cgen@sourceware.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org X-SW-Source: 2012-q1/txt/msg00015.txt.bz2 Hi, I have to implement a development tool chain (assembler, linker etc) for a custom controller with a very special architecture. It has several memory areas and several instruction pointers to them. Each instruction should be spited in such a way that one piece of the instruction goes to one memory section and another piece of the instruction goes into another section. I=E2=80=99m wondering whether CGEN c= an provide a framework for such an unusual architecture. Any ideas are highly appreciated. Sincerely, Lev.