From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 2634 invoked by alias); 3 Feb 2014 17:35:17 -0000 Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org Received: (qmail 2621 invoked by uid 89); 3 Feb 2014 17:35:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qa0-f44.google.com Received: from mail-qa0-f44.google.com (HELO mail-qa0-f44.google.com) (209.85.216.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 03 Feb 2014 17:35:15 +0000 Received: by mail-qa0-f44.google.com with SMTP id w5so10637673qac.31 for ; Mon, 03 Feb 2014 09:35:12 -0800 (PST) X-Received: by 10.224.119.147 with SMTP id z19mr58444925qaq.20.1391448912394; Mon, 03 Feb 2014 09:35:12 -0800 (PST) MIME-Version: 1.0 Received: by 10.140.85.111 with HTTP; Mon, 3 Feb 2014 09:34:52 -0800 (PST) From: Usha Gupta Date: Mon, 03 Feb 2014 17:35:00 -0000 Message-ID: Subject: Help needed for porting opcodes for CISC architecture To: cgen Content-Type: text/plain; charset=ISO-8859-1 X-SW-Source: 2014-q1/txt/msg00003.txt.bz2 Hi All , I am new to CGEN and want to port binutils for a CISC architecture wherein the instruction length can vary from 1 byte to a maximum of 5-bytes. I am having trouble porting opcodes using CGEN. I have defined various hardware elements and instruction fields. I am not sure what should be the values of (default-insn-bitsize 8) (base-insn-bitsize 16) (default-insn-word-bitsize 16 ) (word-bitsize 16 ) As mentioned in the CGEN manual, I specified default-insn bitsize as 8 (smallest instruction length) and rest of the values as 16 ( word length is 2 bytes). This works for 16-bit instructions where both the operands are explicit in the instruction encoding. Another important thing to mention here is that the machine does not have a fixed length opcode. Here are some of the instruction formats : 1-byte instruction: 1) IIIIIrrr - 5 bits opcode , 3 bits for register operand (one of the operand is fixed register, implied from the opcode) 2) IIIddddd - 3 bits opcode, 5 bit displacement 2-byte instruction: 1) IIIIIsss IIIIIttt - 5-bit opcode, 3-bit register operand (source), 5-bit opcode, 3-bit register operand (destination) How do I define instructions of varying length? Any help is appreciated. Thanks and Regards, Usha Gupta