From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x831.google.com (mail-qt1-x831.google.com [IPv6:2607:f8b0:4864:20::831]) by sourceware.org (Postfix) with ESMTPS id E7B80386F828 for ; Wed, 22 Apr 2020 12:31:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org E7B80386F828 Received: by mail-qt1-x831.google.com with SMTP id o10so1442907qtr.6 for ; Wed, 22 Apr 2020 05:31:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=N8yS0L4tU+awXwPZV76Yj4ghTb1PjY9JjxnISs9QL0s=; b=nlT0ep/mYBEqDmbVn+vfOjdazzp6Kf3Vis9dKDERKz11B/irplaOsizqpF5lRQ4h9r nBNMBSq8cWfkGljy+oKICesrYlWchUtlzsspsb1DrhQP6KnLoJ6K++ByCs/ef9TFYP9W A+m53fmwAPOyblxXle4FgLqY6NrgchO25SLP+SM6GOkxFvjp0IcIKxcT4+07RFWodc1h gjr+vU20OuVRr1Z0OaG5nOawKVCuWfApYQjQWgXCGhWJyu217vj0og3cM4AECMOGCbUn OE+HNFKqbD2F+E2cdEat8R1Tl8a0TzLr7fuowzbq0lcLkeLs37mkPSjkHxBQ2C9jO08o 1gZQ== X-Gm-Message-State: AGi0PuZFIUwKmErwwhNsrX8OZifISN2ByiU1d2xr2oGSBjfHls2ahQl+ rQaFyx/9cVrAyfX8xK0D4lz7hR0BTa0Yv7nev0zhExiLUCI= X-Google-Smtp-Source: APiQypLcKkCUlbf5Glv1hRxuErLHD8hghLZGfYyoZzr1hjjeUOFSVDRqu32+pjUy+IiccUm7hWPUsGrzNUEUtO4Of/Y= X-Received: by 2002:ac8:7286:: with SMTP id v6mr26213377qto.299.1587558719063; Wed, 22 Apr 2020 05:31:59 -0700 (PDT) MIME-Version: 1.0 From: Sergey Belyashov Date: Wed, 22 Apr 2020 15:31:48 +0300 Message-ID: Subject: How to define variable size ISA To: cgen@sourceware.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, HTML_MESSAGE, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: cgen@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Cgen mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Apr 2020 12:32:15 -0000 Hi, I trying to rewrite Zilog Z80 CPU support using CGEN. Currently I have implemented one byte instructions. But trying to implement two-byte ones I have an issue: CGEN just check for ORed ifields of first and second bytes (it is not correct), instead of checking for first and than for second one: (dnf f-0 "whole byte 0" ((MACH z80) all-isas) 7 8) (dnf f-1 "whole byte 1" ((MACH z80) all-isas) 15 8) (dnf f-1x "byte 1 field x, bits 7-6" ((MACH z80) all-isas) 15 2) (dnf f-1y "byte 1 field y, bits 5-3" ((MACH z80) all-isas) 13 3) (dnf f-1z "byte 1 field z, bits 2-0" ((MACH z80) all-isas) 10 3) ;RLC (HL) has opcode: 0xCB 0x06 (dni rlc-mhl "rotate left cyclic" (all-isas) "rlc (hl)" (+ (f-0 #xCB) (f-1x 0) (f-1y 0) (f-1z 6)) () ()) (dni rlc-r "rotate left cyclic" (all-isas) "rlc $rs1" (+ (f-0 #xCB) (f-1x 0) (f-1y 0) rs1) () ()) (dni rrc-r "rotate right cyclic" (all-isas) "rrc $rs1" (+ (f-0 #xCB) (f-1x 0) (f-1y 1) rs1) () ()) And disassembler disassemble all CB prefixed instructions as RLC . So it looks like explicit field value is not work. Next I see, what is generated for these instructions in the z80-opc.c file: /* retn */ { { 0, 0, 0, 0 }, { { MNEM, 0 } }, & ifmt_retn, { 0x132 } }, /* rlc $rs1 */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (RS1), 0 } }, & ifmt_rlc_r, { 0xcb } }, /* rlc (hl) */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '(', 'h', 'l', ')', 0 } }, & ifmt_rlc_mhl, { 0xd1 } }, I have two ideas how to workaround it: 1. Switch ISAs on each prefix opcodes (and back after instruction parse finish) and use much of macro instructions for assembler 2. Use fixed 32-bit opcodes and much of C-code hooks and helpers I do not investigate deeply these two cases. I want to know first, it is my mistake, CGEN bug, or undocumented limitation. Best regards, Sergey Belyashov