Hi, I trying to rewrite Zilog Z80 CPU support using CGEN. Currently I have implemented one byte instructions. But trying to implement two-byte ones I have an issue: CGEN just check for ORed ifields of first and second bytes (it is not correct), instead of checking for first and than for second one: (dnf f-0 "whole byte 0" ((MACH z80) all-isas) 7 8) (dnf f-1 "whole byte 1" ((MACH z80) all-isas) 15 8) (dnf f-1x "byte 1 field x, bits 7-6" ((MACH z80) all-isas) 15 2) (dnf f-1y "byte 1 field y, bits 5-3" ((MACH z80) all-isas) 13 3) (dnf f-1z "byte 1 field z, bits 2-0" ((MACH z80) all-isas) 10 3) ;RLC (HL) has opcode: 0xCB 0x06 (dni rlc-mhl "rotate left cyclic" (all-isas) "rlc (hl)" (+ (f-0 #xCB) (f-1x 0) (f-1y 0) (f-1z 6)) () ()) (dni rlc-r "rotate left cyclic" (all-isas) "rlc $rs1" (+ (f-0 #xCB) (f-1x 0) (f-1y 0) rs1) () ()) (dni rrc-r "rotate right cyclic" (all-isas) "rrc $rs1" (+ (f-0 #xCB) (f-1x 0) (f-1y 1) rs1) () ()) And disassembler disassemble all CB prefixed instructions as RLC <r>. So it looks like explicit field value is not work. Next I see, what is generated for these instructions in the z80-opc.c file: /* retn */ { { 0, 0, 0, 0 }, { { MNEM, 0 } }, & ifmt_retn, { 0x132 } }, /* rlc $rs1 */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (RS1), 0 } }, & ifmt_rlc_r, { 0xcb } }, /* rlc (hl) */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '(', 'h', 'l', ')', 0 } }, & ifmt_rlc_mhl, { 0xd1 } }, I have two ideas how to workaround it: 1. Switch ISAs on each prefix opcodes (and back after instruction parse finish) and use much of macro instructions for assembler 2. Use fixed 32-bit opcodes and much of C-code hooks and helpers I do not investigate deeply these two cases. I want to know first, it is my mistake, CGEN bug, or undocumented limitation. Best regards, Sergey Belyashov