From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x841.google.com (mail-qt1-x841.google.com [IPv6:2607:f8b0:4864:20::841]) by sourceware.org (Postfix) with ESMTPS id A362D385B834 for ; Tue, 24 Mar 2020 21:20:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org A362D385B834 Received: by mail-qt1-x841.google.com with SMTP id c9so306875qtw.7 for ; Tue, 24 Mar 2020 14:20:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=SBlIBMX0puLUCusWb5uVhfwdjWlpIb1lcSHk2HFgD/8=; b=lTsTjTnwLleOXOacYL62A+UmrxjbG0WynBAiFJsyDj7iezjPSz/YptSHLyBaR5s1tu BTK1c93qMV0qc4pBFxS7PbC9r+kEsGox8VEdA+eCOir5eX+YXqT5v4ufattJyvxww77s Z4trMt54SsSaxttRGmrLbCGtgNf9ndXqcJ0xagHq8H7Trqyh2Q+0jENG003UW3iAzoBr dHFe8v3xmeSQVrqr7HrfvPrOk2se120fmb/FCxnRDYP6QSkHekuiJHSyG2shC/cOE83S YUHjr/cl8gjwRMujePdGYcQHYFurh5K2lgbVuImVSE96ZlEf+bMTHonjwqcqUUXEyIE4 DyEw== X-Gm-Message-State: ANhLgQ3w/iE3I6JpwlpT7h8tzaYnN5Ysxq3Cu1sEp86IHa8v+TgnCKTv XT5pPByJ2z2NVNECaw++MEOw6nu4qDCbOWdzD2mBhRVP X-Google-Smtp-Source: ADFU+vvpfZNs+A6RWapVxY1DcY//800mrr/2BnpCrq442XDQxDiniiNuqMwrZil2jzYsp4LQggGfZ2tiUuEb7hhc4a0= X-Received: by 2002:ac8:35dd:: with SMTP id l29mr17374935qtb.79.1585084844994; Tue, 24 Mar 2020 14:20:44 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Sergey Belyashov Date: Wed, 25 Mar 2020 00:20:33 +0300 Message-ID: Subject: Re: Writing .cpu file for Z80 To: cgen@sourceware.org X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, HTML_MESSAGE, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: cgen@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Cgen mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Mar 2020 21:20:47 -0000 Hi, Today I try to implement 0xCB prefixed instructions. I add next instructions: (dnf f-0 "whole byte 0" ((MACH z80) all-isas) 7 8) (dnf f-1 "whole byte 1" ((MACH z80) all-isas) 15 8) (dnf f-1x "byte 1 field x, bits 7-6" ((MACH z80) all-isas) 15 2) (dnf f-1y "byte 1 field y, bits 5-3" ((MACH z80) all-isas) 13 3) (dnf f-1z "byte 1 field z, bits 2-0" ((MACH z80) all-isas) 10 3) (dni rlc-mhl "rotate left cyclic" (all-isas) "rlc (hl)" (+ (f-0 #xCB) (f-1x 0) (f-1y 0) (f-1z 6)) () ()) (dni rlc-r "rotate left cyclic" (all-isas) "rlc $rs1" (+ (f-0 #xCB) (f-1x 0) (f-1y 0) rs1) () ()) (dni rrc-r "rotate right cyclic" (all-isas) "rrc $rs1" (+ (f-0 #xCB) (f-1x 0) (f-1y 1) rs1) () ()) And disassembler disassemble all CB prefixed instructions as RLC . So it looks like explicit field value is not work. Next I see, what is generated for these instructions in the z80-opc.c file: /* retn */ { { 0, 0, 0, 0 }, { { MNEM, 0 } }, & ifmt_retn, { 0x132 } }, /* rlc $rs1 */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (RS1), 0 } }, & ifmt_rlc_r, { 0xcb } }, /* rlc (hl) */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '(', 'h', 'l', ')', 0 } }, & ifmt_rlc_mhl, { 0xd1 } }, Why fields of different bytes are OR'ed?!? Next, I try to specify following decode-splits for ISA: (decode-splits (f-y () ((s-reg8 (0 1 2 3 4 5 7)) (s-mhl (6)))) (f-z () ((s-reg8 (0 1 2 3 4 5 7)) (s-mhl (6)))) ) But CGEN fails with error: machs: all isas: all options: trace: diags: Including file ../../opcodes/../cpu/simplify.inc ... ERROR: Wrong type argument in position 2: 3 No backtrace available. decode-splits is present only one arm.cpu file, but it commented out. Is it works? Best regards, Sergey Belyashov =D0=B2=D1=82, 24 =D0=BC=D0=B0=D1=80. 2020 =D0=B3. =D0=B2 00:44, Sergey Bely= ashov : > Hi, > I trying to write .cpu file for Z80. Now I stopped in place, how to > implement multibyte opcodes. Z80 instructions may have size from one byte > to four bytes: > [|] > <0xED> [|] > <0xCB> > <0xDD/0xFD> <0xCB> > <0xDD/0xFD> [||] > <0xDD/0xFD> > > First format is implemented, now I try second one. Starting from simple > instruction RETN (ED 45): > (dnf f-0 "whole byte 0" ((MACH z80) all-isas) 7 8) > (dnf f-1 "whole byte 1" ((MACH z80) all-isas) 15 8) > (dni retn "return from NMI handler" (all-isas UNCOND-CTI) "retn" (+ > (f-0 #xED) (f-1 #x45)) () ()) > > But disassembler do not disassemble 0xED 0x45 sequence. I try declare > opcode as one 16-bit field, but CGEN fails: > > Error: Instruction has opcode bits outside of its mask. > > This usually means some kind of error in the instruction's ifield list. > > base mask: 0xffff, base value: 0xed45 > > field list: (f-xx 15 16) > > What I'm doing wrong? > > whole .cpu file is available here: > https://github.com/b-s-a/binutils-gdb/tree/z80-cgen/cpu > > Best regards, > Sergey Belyashov >