From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1572 invoked by alias); 21 Feb 2020 14:51:28 -0000 Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org Received: (qmail 1559 invoked by uid 89); 21 Feb 2020 14:51:28 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_1,HTML_MESSAGE,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=lil, undocumented, HTo:U*cgen, H*Ad:U*cgen X-HELO: mail-qt1-f171.google.com Received: from mail-qt1-f171.google.com (HELO mail-qt1-f171.google.com) (209.85.160.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 21 Feb 2020 14:51:26 +0000 Received: by mail-qt1-f171.google.com with SMTP id w47so1432182qtk.4 for ; Fri, 21 Feb 2020 06:51:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=mbPlZD6QdVvwQZQGEUPiaXduQ4yU5uFJ3XyxSdzQdyU=; b=oFKyVABKxxdIZhIPlP5mbNBLtyAtIpYJiMv2V+a/kJZoRcmkw4/UqwwCLlbZyr/A87 eK0yf+Xwk3YD21ORrNkyh7+NCqwVwqpZQdc8AifGmag2ug7f0EpOGSKvo1JyqqymAfan oujCAWnraLijF1QxmdCdlFmY0UTBXM2gMRsE8Aj/30Vi3DQzrPLKQYOe0yY8P6OmIJk3 CamshJnBu+YHsiFxekZQMynqFcR1xc4Kb1hIMTEeillqusfLB0GdNxvvRFN488rZOIt+ +k0Pj+hrebJTdhlGCWpGu7B+2Yuu0M+PxYCl85UoP2AxcMGi/ldkQgI6aHfu86OVEjnk R4tg== MIME-Version: 1.0 From: Sergey Belyashov Date: Fri, 21 Feb 2020 14:51:00 -0000 Message-ID: Subject: Writing .cpu file for Z80 To: cgen@sourceware.org Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2020-q1/txt/msg00011.txt Hi, I want to rewrite Z80 port using CGEN. And I have following questions: The Z80 CPU uses prefix opcodes to change opcode tables and operation registers. For example, <0x21 0x34 0x12> is "LD HL,0x1234", but <0xdd 0x21 0x34 0x12> is "LD IX,0x1234". Do I need write both instructions or is it possible to write rule which selects proper instruction set or extract correct register index? Z80 has special rule to form indirect memory operations using index registers. There immediate offset is always third byte of instruction. For example: <0xdd 0x34 0x12> is "INC (IX+0x12)", <0xfd 0x36 0xfe 0xab> is "LD (IY-0x02),0xAB"... But there are "strange" instructions, where index is placed before opcode itself: <0xdd 0xcb 0x10 0x1e> is "RR (IX+0x10)" (<0xcb 0x1e> is "RR (HL)", <0xcb> is opcode prefix, which select another opcode table) and undocumented one <0xdd 0xcb 0x10 0x1f> "RR (IX+0x10),A". Should I write 2 instructions types? eZ80 uses four opcode prefixes (.SIS, .SIL, .LIS, .LIL) which set operation mode (.IL - long instruction (24 bit immediate), .IS - short instruction (16 bit immediate), .S - 16 bit processing, .L - 24 bit processing): <0x40 0x21 0x34 0x12> is "LD.SIS HL,0x1234" and <0x5b 0x21 0x56 0x34 0x12> is "LD.LIL HL,0x123456". These prefixes can be applied to all instructions (but it has no sense for part of instructions). Moreover, assembler should support short mode of instructions (.S, .L, .IS, .IL), which is completed by assembler depending on compiling mode (ADL or Z80). Should I generate all possible combinations (9 x instruction_set)? Is there more correct solution? Best regards, Sergey Belyashov