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* Writing .cpu file for Z80
@ 2020-02-21 14:51 Sergey Belyashov
  2020-02-22 15:11 ` Frank Ch. Eigler
  0 siblings, 1 reply; 6+ messages in thread
From: Sergey Belyashov @ 2020-02-21 14:51 UTC (permalink / raw)
  To: cgen

Hi,
I want to rewrite Z80 port using CGEN. And I have following questions:

The Z80 CPU uses prefix opcodes to change opcode tables and operation
registers. For example, <0x21 0x34 0x12> is "LD HL,0x1234", but <0xdd 0x21
0x34 0x12> is "LD IX,0x1234". Do I need write both instructions or is it
possible to write rule which selects proper instruction set or extract
correct register index?

Z80 has special rule to form indirect memory operations using index
registers. There immediate offset is always third byte of instruction. For
example: <0xdd 0x34 0x12> is "INC (IX+0x12)", <0xfd 0x36 0xfe 0xab> is "LD
(IY-0x02),0xAB"... But there are "strange" instructions, where index is
placed before opcode itself: <0xdd 0xcb 0x10 0x1e> is "RR (IX+0x10)" (<0xcb
0x1e> is "RR (HL)", <0xcb> is opcode prefix, which select another opcode
table) and undocumented one <0xdd 0xcb 0x10 0x1f> "RR (IX+0x10),A". Should
I write 2 instructions types?

eZ80 uses four opcode prefixes (.SIS, .SIL, .LIS, .LIL) which set operation
mode (.IL - long instruction (24 bit immediate), .IS - short instruction
(16 bit immediate), .S - 16 bit processing, .L - 24 bit processing): <0x40
0x21 0x34 0x12> is "LD.SIS HL,0x1234" and <0x5b 0x21 0x56 0x34 0x12> is
"LD.LIL HL,0x123456".  These prefixes can be applied to all instructions
(but it has no sense for part of instructions). Moreover, assembler should
support short mode of instructions (.S, .L, .IS, .IL), which is completed
by assembler depending on compiling mode (ADL or Z80). Should I generate
all possible combinations (9 x instruction_set)? Is there more correct
solution?

Best regards,
Sergey Belyashov

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Writing .cpu file for Z80
@ 2020-03-23 21:44 Sergey Belyashov
  2020-03-24 21:20 ` Sergey Belyashov
  0 siblings, 1 reply; 6+ messages in thread
From: Sergey Belyashov @ 2020-03-23 21:44 UTC (permalink / raw)
  To: cgen

Hi,
I trying to write .cpu file for Z80. Now I stopped in place, how to
implement multibyte opcodes. Z80 instructions may have size from one byte
to four bytes:
<opcode> [<imm8>|<imm16>]
<0xED> <opcode> [<imm8>|<imm16>]
<0xCB> <opcode>
<0xDD/0xFD> <0xCB> <disp8> <opcode>
<0xDD/0xFD> <opcode> [<imm8>|<disp8>|<imm16>]
<0xDD/0xFD> <opcode> <disp8> <imm8>

First format is implemented, now I try second one. Starting from simple
instruction RETN (ED 45):
(dnf f-0 "whole byte 0" ((MACH z80) all-isas) 7 8)
(dnf f-1  "whole byte 1" ((MACH z80) all-isas) 15 8)
(dni retn       "return from NMI handler" (all-isas UNCOND-CTI) "retn" (+
(f-0 #xED) (f-1 #x45)) () ())

But disassembler do not disassemble 0xED 0x45 sequence. I try declare
opcode as one 16-bit field, but CGEN fails:
> Error: Instruction has opcode bits outside of its mask.
> This usually means some kind of error in the instruction's ifield list.
> base mask: 0xffff, base value: 0xed45
> field list: (f-xx 15 16)

What I'm doing wrong?

whole .cpu file is available here:
https://github.com/b-s-a/binutils-gdb/tree/z80-cgen/cpu

Best regards,
Sergey Belyashov

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2020-03-24 21:20 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-21 14:51 Writing .cpu file for Z80 Sergey Belyashov
2020-02-22 15:11 ` Frank Ch. Eigler
2020-02-22 19:19   ` Sergey Belyashov
2020-02-23  0:03     ` Frank Ch. Eigler
2020-03-23 21:44 Sergey Belyashov
2020-03-24 21:20 ` Sergey Belyashov

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