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From: Sergey Belyashov <sergey.belyashov@gmail.com>
Date: Tue, 24 Mar 2020 00:44:27 +0300
Message-ID: <CAOe0RDxvHb73a9cWmr4UsQUj5PpirA-ZMPm2NEuu_KLv0b4vdA@mail.gmail.com>
Subject: Writing .cpu file for Z80
To: cgen@sourceware.org
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Hi,
I trying to write .cpu file for Z80. Now I stopped in place, how to
implement multibyte opcodes. Z80 instructions may have size from one byte
to four bytes:
<opcode> [<imm8>|<imm16>]
<0xED> <opcode> [<imm8>|<imm16>]
<0xCB> <opcode>
<0xDD/0xFD> <0xCB> <disp8> <opcode>
<0xDD/0xFD> <opcode> [<imm8>|<disp8>|<imm16>]
<0xDD/0xFD> <opcode> <disp8> <imm8>

First format is implemented, now I try second one. Starting from simple
instruction RETN (ED 45):
(dnf f-0 "whole byte 0" ((MACH z80) all-isas) 7 8)
(dnf f-1  "whole byte 1" ((MACH z80) all-isas) 15 8)
(dni retn       "return from NMI handler" (all-isas UNCOND-CTI) "retn" (+
(f-0 #xED) (f-1 #x45)) () ())

But disassembler do not disassemble 0xED 0x45 sequence. I try declare
opcode as one 16-bit field, but CGEN fails:
> Error: Instruction has opcode bits outside of its mask.
> This usually means some kind of error in the instruction's ifield list.
> base mask: 0xffff, base value: 0xed45
> field list: (f-xx 15 16)

What I'm doing wrong?

whole .cpu file is available here:
https://github.com/b-s-a/binutils-gdb/tree/z80-cgen/cpu

Best regards,
Sergey Belyashov