From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf29.google.com (mail-qv1-xf29.google.com [IPv6:2607:f8b0:4864:20::f29]) by sourceware.org (Postfix) with ESMTPS id 499DA3858D35 for ; Thu, 30 Jul 2020 09:11:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 499DA3858D35 Received: by mail-qv1-xf29.google.com with SMTP id dd12so7159661qvb.0 for ; Thu, 30 Jul 2020 02:11:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=2nw/K1sPCMFiXE7WDfn3MkkePdhak9SeTwaAKpJL3wU=; b=U3X/cFCoxh9vOo6+eYoZKgbwGys3Z3SvlaJmwxUkyGtygUINNvPXIibN2RHYCfT63F 3l9jHKrTun7WwctlXNgZbD82WTvCGFJj085xOwZOdydIYW8jJDTUsmt4S0riy8rv0U2k q1Ln0337igD1yN9wk8RyRpSWPc5humXz5+w3Gz8kSst9NIWO/mZQQxcOB7rRY0IoB2w0 PugrQ6mJjuMOvOzfI6U3aTDUCg5QT5a81D9DUg+ZIb2kMmcz8abZx95n7ZIt82F58Yoo XR2g0mDXpQZtsRwe1P/ywg8oHzipTHqiYXYD1a923u/CTItpzDxL/8Lry5RU0hUdzk1x vz+A== X-Gm-Message-State: AOAM532UZcIr6EOYmgrCJweZxySs+fUEdbq00eKRyJftl93h6+WEhXxt RS0rga7xrd6spukqfRDxoUO+Cn0pu6vQeIW6MLNspd4X X-Google-Smtp-Source: ABdhPJycHA+z512cNaRBl0wiuSp4+0w2K2F2z9yfiAB3SO0LMiqc06fWlB3lm/HKPbG/UzqeAigsMEHH5PTexUrAWnc= X-Received: by 2002:a0c:e912:: with SMTP id a18mr1894690qvo.226.1596100314514; Thu, 30 Jul 2020 02:11:54 -0700 (PDT) MIME-Version: 1.0 References: <20200427162914.GA21677@redhat.com> <87pnbsztze.fsf@gnu.org> <87lfmgzoic.fsf@gnu.org> In-Reply-To: From: Sergey Belyashov Date: Thu, 30 Jul 2020 12:11:43 +0300 Message-ID: Subject: Re: BUG: non-fixed-length ISAs are unsupported for now To: Sergey Belyashov via Cgen Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: cgen@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Cgen mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Jul 2020 09:11:56 -0000 Hi, Can anybody help me, how to correctly implement Zilog Z80 (and derivatives) instruction decode table switching in CGEN? For example, the main table has 1 byte instruction and possibly 1-2 bytes of immediate operand. There are four (ez80 has eight) pseudo instructions which switches tables for current instruction: * 0xCB - next byte is rotation or bit manipulation instruction code, no optional operands; * 0xED - next byte is instruction of extended instruction set, possible 1-2 bytes of immediate operand; * 0xDD/0xFD - switches use of H, L and HL registers to IX/IY on main and 0xCB tables (here is difficult, because always added immediate before instruction code: 0xDD 0xCB 0x07 0x3E - "srl (ix+7)"). I think, it should be done in following way: * it is need to create 5 ISAs: isa_00, isa_cb, isa_ed, isa_ii_00, isa_ii_cb * opcodes 0xCB, 0xDD, 0xED, 0xFD just switches ISA for current instruction * Best regards, Sergey Belyashov