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From: Sergey Belyashov <sergey.belyashov@gmail.com>
Date: Wed, 12 Aug 2020 22:19:43 +0300
Message-ID: <CAOe0RDyi+mPUtqkcFuP7d80QS4+on=ogjhrP3VYA-iafUsRS8Q@mail.gmail.com>
Subject: Re: BUG: non-fixed-length ISAs are unsupported for now
To: "Jose E. Marchesi" <jose.marchesi@oracle.com>
Cc: "Frank Ch. Eigler via Cgen" <cgen@sourceware.org>,
 "Frank Ch. Eigler" <fche@redhat.com>
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But Zilog eZ80 CPU has instructions up to 6 bytes long: like ld.il bc,(Mmn)
(lil/sil prefix 0xed prefix <opcode> <n> <m> <M>) .

=D1=81=D1=80, 12 =D0=B0=D0=B2=D0=B3. 2020 =D0=B3., 21:53 Jose E. Marchesi <=
jose.marchesi@oracle.com>:

>
> >> I have tried it. Result is the same: ifields are just added (part of
> >> generated z80-opc.c):
> >
> > I'm unfortunately unable to actually run cgen here (apparent
> > incompatibility with "new" fedora32-level guile), so am only guessing
> > that you could try setting the cpu base-insn-size to 16 or even 32:
> > enough bits to tell the instructions apart.
>
> That looks like the right approach.
>
> Currently CGEN does not support having opcodes (constant fields) past
> the base part of the insn, which by the way is limited to a maximum of
> 32-bit.