Whilst trying to get eCos to run on SID, I realised it was failing due to a LDMIA instruction not being emulated in the CPU simulator. Here is a patch to complete the combinations of LDM/STM instructions which are missing in CGEN for the ARM7. I have a feeling that it could be implemented more efficiently, but I am somewhat a newbie to Scheme, and also to contributing patches in the GNU manner, so please bear with me. I have run the testsuite by doing the following: cd build/sid/component/testsuite make check This failed, so I ran it manually: runtest --tool sidcomp --srcdir ../../../../src/sid/component/testsuite 'sidcomp.sum' is attached. Note that there are failures in the CPU monkey tests, but these also occur using the original build. I have also verified it by successfully running a program similar to the eCos 'twothreads' example. To fully update SID, the following needs to be done: cd build/sid/component/cgen-cpu/arm7t make cgen-all cd ../../../ make all install Robert Cragie, Design Engineer _______________________________________________________________ Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK http://www.jennic.com Tel: +44 (0) 114 281 2655 [src/cgen/cpu] 2002-08-29 Robert Cragie * arm7.cpu (ldm*-sw-action): New pmacros to support LDM insns * arm7.cpu (ldm*-sw-action-r15): New pmacros to support LDM insns * arm7.cpu (ldm*-sw): New LDM insn macros (PUSWL = xxSwL) * arm7.cpu (ldm*-sw-wb): New LDM insn macros (PUSWL = xxSWL) * arm7.cpu (stm*-sw-action): New pmacros to support STM insns * arm7.cpu (stm*-sw): New STM insn macros (PUSWL = xxSwl) * arm7.cpu (stm*-sw-wb): New STM insn macros (PUSWL = xxSWl) Index: cgen/cpu/arm7.cpu =================================================================== RCS file: /cvs/src/src/cgen/cpu/arm7.cpu,v retrieving revision 1.1 diff -u -p -r1.1 arm7.cpu --- cgen/cpu/arm7.cpu 5 Jul 2001 12:45:47 -0000 1.1 +++ cgen/cpu/arm7.cpu 29 Aug 2002 10:10:46 -0000 @@ -1453,6 +1453,21 @@ (set addr (sub addr 4))) ) +(define-pmacro (ldmda-sw-action bit-num) + (sequence () + (if (and reglist (sll 1 15)) + (set (reg WI h-gr bit-num) (mem WI addr)) + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr))) + (set addr (sub addr 4))) +) + +(define-pmacro (ldmda-sw-action-r15 ignored) + (sequence () + (set pc (mem WI addr)) + (set addr (sub addr 4)) + (set (reg h-cpsr) (reg h-spsr))) +) + (dnai ldmda "Load multiple registers (postindex, decrement)" () "FIXME" @@ -1479,6 +1494,32 @@ ) ) +(dnai ldmda-sw "Load multiple registers (postindex, decrement, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 0) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 ldmda-sw-action-r15) + (multi-action 14 ldmda-sw-action) + (multi-action 13 ldmda-sw-action) + (multi-action 12 ldmda-sw-action) + (multi-action 11 ldmda-sw-action) + (multi-action 10 ldmda-sw-action) + (multi-action 9 ldmda-sw-action) + (multi-action 8 ldmda-sw-action) + (multi-action 7 ldmda-action) + (multi-action 6 ldmda-action) + (multi-action 5 ldmda-action) + (multi-action 4 ldmda-action) + (multi-action 3 ldmda-action) + (multi-action 2 ldmda-action) + (multi-action 1 ldmda-action) + (multi-action 0 ldmda-action) + ) +) + (dnai ldmda-wb "Load multiple registers (postindex, decrement, writeback)" () "FIXME" @@ -1505,6 +1546,32 @@ (set rn addr)) ) +(dnai ldmda-sw-wb "Load multiple registers (postindex, decrement, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 1) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 ldmda-sw-action-r15) + (multi-action 14 ldmda-sw-action) + (multi-action 13 ldmda-sw-action) + (multi-action 12 ldmda-sw-action) + (multi-action 11 ldmda-sw-action) + (multi-action 10 ldmda-sw-action) + (multi-action 9 ldmda-sw-action) + (multi-action 8 ldmda-sw-action) + (multi-action 7 ldmda-action) + (multi-action 6 ldmda-action) + (multi-action 5 ldmda-action) + (multi-action 4 ldmda-action) + (multi-action 3 ldmda-action) + (multi-action 2 ldmda-action) + (multi-action 1 ldmda-action) + (multi-action 0 ldmda-action) + (set rn addr)) +) + (define-pmacro (ldmib-action bit-num) (sequence () (set addr (add addr 4)) @@ -1517,6 +1584,21 @@ (set pc (mem WI addr))) ) +(define-pmacro (ldmib-sw-action bit-num) + (sequence () + (set addr (add addr 4)) + (if (and reglist (sll 1 15)) + (set (reg WI h-gr bit-num) (mem WI addr)) + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr)))) +) + +(define-pmacro (ldmib-sw-action-r15 ignored) + (sequence () + (set addr (add addr 4)) + (set pc (mem WI addr)) + (set (reg h-cpsr) (reg h-spsr))) +) + (dnai ldmib "Load multiple register (preindex, increment)" () "FIXME" @@ -1542,6 +1624,31 @@ (multi-action 15 ldmib-action-r15)) ) +(dnai ldmib-sw "Load multiple register (preindex, increment, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 0) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 ldmib-action) + (multi-action 1 ldmib-action) + (multi-action 2 ldmib-action) + (multi-action 3 ldmib-action) + (multi-action 4 ldmib-action) + (multi-action 5 ldmib-action) + (multi-action 6 ldmib-action) + (multi-action 7 ldmib-action) + (multi-action 8 ldmib-sw-action) + (multi-action 9 ldmib-sw-action) + (multi-action 10 ldmib-sw-action) + (multi-action 11 ldmib-sw-action) + (multi-action 12 ldmib-sw-action) + (multi-action 13 ldmib-sw-action) + (multi-action 14 ldmib-sw-action) + (multi-action 15 ldmib-sw-action-r15)) +) + (dnai ldmib-wb "Load multiple registers (preindex, increment, writeback)" () "FIXME" @@ -1568,6 +1675,32 @@ (set rn addr)) ) +(dnai ldmib-sw-wb "Load multiple registers (preindex, increment, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 1) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 ldmib-action) + (multi-action 1 ldmib-action) + (multi-action 2 ldmib-action) + (multi-action 3 ldmib-action) + (multi-action 4 ldmib-action) + (multi-action 5 ldmib-action) + (multi-action 6 ldmib-action) + (multi-action 7 ldmib-action) + (multi-action 8 ldmib-sw-action) + (multi-action 9 ldmib-sw-action) + (multi-action 10 ldmib-sw-action) + (multi-action 11 ldmib-sw-action) + (multi-action 12 ldmib-sw-action) + (multi-action 13 ldmib-sw-action) + (multi-action 14 ldmib-sw-action) + (multi-action 15 ldmib-sw-action-r15) + (set rn addr)) +) + (define-pmacro (ldmia-action bit-num) (sequence () (set (reg WI h-gr bit-num) (mem WI addr)) @@ -1580,6 +1713,21 @@ (set addr (add addr 4))) ) +(define-pmacro (ldmia-sw-action bit-num) + (sequence () + (if (and reglist (sll 1 15)) + (set (reg WI h-gr bit-num) (mem WI addr)) + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr))) + (set addr (add addr 4))) +) + +(define-pmacro (ldmia-sw-action-r15 ignored) + (sequence () + (set pc (mem WI addr)) + (set addr (add addr 4)) + (set (reg h-cpsr) (reg h-spsr))) +) + (dnai ldmia "Load multiple registers (postindex, increment)" () "FIXME" @@ -1605,6 +1753,31 @@ (multi-action 15 ldmia-action-r15)) ) +(dnai ldmia-sw "Load multiple registers (postindex, increment, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 0) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 ldmia-action) + (multi-action 1 ldmia-action) + (multi-action 2 ldmia-action) + (multi-action 3 ldmia-action) + (multi-action 4 ldmia-action) + (multi-action 5 ldmia-action) + (multi-action 6 ldmia-action) + (multi-action 7 ldmia-action) + (multi-action 8 ldmia-sw-action) + (multi-action 9 ldmia-sw-action) + (multi-action 10 ldmia-sw-action) + (multi-action 11 ldmia-sw-action) + (multi-action 12 ldmia-sw-action) + (multi-action 13 ldmia-sw-action) + (multi-action 14 ldmia-sw-action) + (multi-action 15 ldmia-sw-action-r15)) +) + (dnai ldmia-wb "Load multiple registers (postindex, increment, writeback)" () "FIXME" @@ -1631,6 +1804,32 @@ (set rn addr)) ) +(dnai ldmia-sw-wb "Load multiple registers (postindex, increment, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 1) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 ldmia-action) + (multi-action 1 ldmia-action) + (multi-action 2 ldmia-action) + (multi-action 3 ldmia-action) + (multi-action 4 ldmia-action) + (multi-action 5 ldmia-action) + (multi-action 6 ldmia-action) + (multi-action 7 ldmia-action) + (multi-action 8 ldmia-sw-action) + (multi-action 9 ldmia-sw-action) + (multi-action 10 ldmia-sw-action) + (multi-action 11 ldmia-sw-action) + (multi-action 12 ldmia-sw-action) + (multi-action 13 ldmia-sw-action) + (multi-action 14 ldmia-sw-action) + (multi-action 15 ldmia-sw-action-r15) + (set rn addr)) +) + (define-pmacro (ldmdb-action bit-num) (sequence () (set addr (sub addr 4)) @@ -1643,6 +1842,21 @@ (set pc (mem WI addr))) ) +(define-pmacro (ldmdb-sw-action bit-num) + (sequence () + (set addr (sub addr 4)) + (if (and reglist (sll 1 15)) + (set (reg WI h-gr bit-num) (mem WI addr)) + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr)))) +) + +(define-pmacro (ldmdb-sw-action-r15 ignored) + (sequence () + (set addr (sub addr 4)) + (set pc (mem WI addr)) + (set (reg h-cpsr) (reg h-spsr))) +) + (dnai ldmdb "Load multiple registers (preindex, decrement)" () "ldm$cond .." @@ -1668,6 +1882,31 @@ (multi-action 0 ldmdb-action)) ) +(dnai ldmdb-sw "Load multiple registers (preindex, decrement, switch)" + () + "ldm$cond .." + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 0) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 ldmdb-sw-action-r15) + (multi-action 14 ldmdb-sw-action) + (multi-action 13 ldmdb-sw-action) + (multi-action 12 ldmdb-sw-action) + (multi-action 11 ldmdb-sw-action) + (multi-action 10 ldmdb-sw-action) + (multi-action 9 ldmdb-sw-action) + (multi-action 8 ldmdb-sw-action) + (multi-action 7 ldmdb-action) + (multi-action 6 ldmdb-action) + (multi-action 5 ldmdb-action) + (multi-action 4 ldmdb-action) + (multi-action 3 ldmdb-action) + (multi-action 2 ldmdb-action) + (multi-action 1 ldmdb-action) + (multi-action 0 ldmdb-action)) +) + (dnai ldmdb-wb "Load multiple registers (preindex, decrement, writeback)" () "FIXME" @@ -1694,12 +1933,46 @@ (set rn addr)) ) +(dnai ldmdb-sw-wb "Load multiple registers (preindex, decrement, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 1) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 ldmdb-sw-action-r15) + (multi-action 14 ldmdb-sw-action) + (multi-action 13 ldmdb-sw-action) + (multi-action 12 ldmdb-sw-action) + (multi-action 11 ldmdb-sw-action) + (multi-action 10 ldmdb-sw-action) + (multi-action 9 ldmdb-sw-action) + (multi-action 8 ldmdb-sw-action) + (multi-action 7 ldmdb-action) + (multi-action 6 ldmdb-action) + (multi-action 5 ldmdb-action) + (multi-action 4 ldmdb-action) + (multi-action 3 ldmdb-action) + (multi-action 2 ldmdb-action) + (multi-action 1 ldmdb-action) + (multi-action 0 ldmdb-action) + (set rn addr)) +) + (define-pmacro (stmdb-action bit-num) (sequence () (set addr (sub addr 4)) (set (mem WI addr) (reg WI h-gr bit-num))) ) +(define-pmacro (stmdb-sw-action bit-num) + (sequence () + (set addr (sub addr 4)) + (if (and reglist (sll 1 15)) + (set (mem WI addr) (reg WI h-gr bit-num)) + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8))))) +) + (define-pmacro (stmdb-action-r15 ignore) (sequence () (set addr (sub addr 4)) @@ -1731,6 +2004,31 @@ (multi-action 0 stmdb-action)) ) +(dnai stmdb-sw "Store multiple registers (preindex, decrement, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 0) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 stmdb-action-r15) + (multi-action 14 stmdb-sw-action) + (multi-action 13 stmdb-sw-action) + (multi-action 12 stmdb-sw-action) + (multi-action 11 stmdb-sw-action) + (multi-action 10 stmdb-sw-action) + (multi-action 9 stmdb-sw-action) + (multi-action 8 stmdb-sw-action) + (multi-action 7 stmdb-action) + (multi-action 6 stmdb-action) + (multi-action 5 stmdb-action) + (multi-action 4 stmdb-action) + (multi-action 3 stmdb-action) + (multi-action 2 stmdb-action) + (multi-action 1 stmdb-action) + (multi-action 0 stmdb-action)) +) + (dnai stmdb-wb "Store multiple registers (preindex, decrement, writeback)" () "FIXME" @@ -1757,12 +2055,46 @@ (set rn addr)) ) +(dnai stmdb-sw-wb "Store multiple registers (preindex, decrement, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 1) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 stmdb-action-r15) + (multi-action 14 stmdb-sw-action) + (multi-action 13 stmdb-sw-action) + (multi-action 12 stmdb-sw-action) + (multi-action 11 stmdb-sw-action) + (multi-action 10 stmdb-sw-action) + (multi-action 9 stmdb-sw-action) + (multi-action 8 stmdb-sw-action) + (multi-action 7 stmdb-action) + (multi-action 6 stmdb-action) + (multi-action 5 stmdb-action) + (multi-action 4 stmdb-action) + (multi-action 3 stmdb-action) + (multi-action 2 stmdb-action) + (multi-action 1 stmdb-action) + (multi-action 0 stmdb-action) + (set rn addr)) +) + (define-pmacro (stmib-action bit-num) (sequence () (set addr (add addr 4)) (set (mem WI addr) (reg WI h-gr bit-num))) ) +(define-pmacro (stmib-sw-action bit-num) + (sequence () + (set addr (add addr 4)) + (if (and reglist (sll 1 15)) + (set (mem WI addr) (reg WI h-gr bit-num)) + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8))))) +) + (define-pmacro (stmib-action-r15 ignore) (sequence () (set addr (add addr 4)) @@ -1794,6 +2126,31 @@ (multi-action 15 stmib-action-r15)) ) +(dnai stmib-sw "Store multiple registers (preindex, increment, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 0) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 stmib-action) + (multi-action 1 stmib-action) + (multi-action 2 stmib-action) + (multi-action 3 stmib-action) + (multi-action 4 stmib-action) + (multi-action 5 stmib-action) + (multi-action 6 stmib-action) + (multi-action 7 stmib-action) + (multi-action 8 stmib-sw-action) + (multi-action 9 stmib-sw-action) + (multi-action 10 stmib-sw-action) + (multi-action 11 stmib-sw-action) + (multi-action 12 stmib-sw-action) + (multi-action 13 stmib-sw-action) + (multi-action 14 stmib-sw-action) + (multi-action 15 stmib-action-r15)) +) + (dnai stmib-wb "Store multiple registers (preindex, increment, writeback)" () "FIXME" @@ -1820,12 +2177,46 @@ (set rn addr)) ) +(dnai stmib-sw-wb "Store multiple registers (preindex, increment, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 1) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 stmib-action) + (multi-action 1 stmib-action) + (multi-action 2 stmib-action) + (multi-action 3 stmib-action) + (multi-action 4 stmib-action) + (multi-action 5 stmib-action) + (multi-action 6 stmib-action) + (multi-action 7 stmib-action) + (multi-action 8 stmib-sw-action) + (multi-action 9 stmib-sw-action) + (multi-action 10 stmib-sw-action) + (multi-action 11 stmib-sw-action) + (multi-action 12 stmib-sw-action) + (multi-action 13 stmib-sw-action) + (multi-action 14 stmib-sw-action) + (multi-action 15 stmib-action-r15) + (set rn addr)) +) + (define-pmacro (stmia-action bit-num) (sequence () (set (mem WI addr) (reg WI h-gr bit-num)) (set addr (add addr 4))) ) +(define-pmacro (stmia-sw-action bit-num) + (sequence () + (if (and reglist (sll 1 15)) + (set (mem WI addr) (reg WI h-gr bit-num)) + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8)))) + (set addr (add addr 4))) +) + (define-pmacro (stmia-action-r15 ignore) (sequence () (set (mem WI addr) (add (reg WI h-gr 15) 4)) @@ -1857,6 +2248,31 @@ (multi-action 15 stmia-action-r15)) ) +(dnai stmia-sw "Store multiple registers (postindex, increment, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 0) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 stmia-action) + (multi-action 1 stmia-action) + (multi-action 2 stmia-action) + (multi-action 3 stmia-action) + (multi-action 4 stmia-action) + (multi-action 5 stmia-action) + (multi-action 6 stmia-action) + (multi-action 7 stmia-action) + (multi-action 8 stmia-sw-action) + (multi-action 9 stmia-sw-action) + (multi-action 10 stmia-sw-action) + (multi-action 11 stmia-sw-action) + (multi-action 12 stmia-sw-action) + (multi-action 13 stmia-sw-action) + (multi-action 14 stmia-sw-action) + (multi-action 15 stmia-action-r15)) +) + (dnai stmia-wb "Store multiple registers (postindex, increment, writeback)" () "FIXME" @@ -1883,12 +2299,46 @@ (set rn addr)) ) +(dnai stmia-sw-wb "Store multiple registers (postindex, increment, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 1) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 stmia-action) + (multi-action 1 stmia-action) + (multi-action 2 stmia-action) + (multi-action 3 stmia-action) + (multi-action 4 stmia-action) + (multi-action 5 stmia-action) + (multi-action 6 stmia-action) + (multi-action 7 stmia-action) + (multi-action 8 stmia-sw-action) + (multi-action 9 stmia-sw-action) + (multi-action 10 stmia-sw-action) + (multi-action 11 stmia-sw-action) + (multi-action 12 stmia-sw-action) + (multi-action 13 stmia-sw-action) + (multi-action 14 stmia-sw-action) + (multi-action 15 stmia-action-r15) + (set rn addr)) +) + (define-pmacro (stmda-action-r15 ignore) (sequence () (set (mem WI addr) (add (reg WI h-gr 15) 4)) (set addr (sub addr 4))) ) +(define-pmacro (stmda-sw-action bit-num) + (sequence () + (if (and reglist (sll 1 15)) + (set (mem WI addr) (reg WI h-gr bit-num)) + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8)))) + (set addr (sub addr 4))) +) + (define-pmacro (stmda-action bit-num) (sequence () (set (mem WI addr) (reg WI h-gr bit-num)) @@ -1920,6 +2370,31 @@ (multi-action 0 stmda-action)) ) +(dnai stmda-sw "Store multiple registers (postindex, decrement, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 0) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 stmda-action-r15) + (multi-action 14 stmda-sw-action) + (multi-action 13 stmda-sw-action) + (multi-action 12 stmda-sw-action) + (multi-action 11 stmda-sw-action) + (multi-action 10 stmda-sw-action) + (multi-action 9 stmda-sw-action) + (multi-action 8 stmda-sw-action) + (multi-action 7 stmda-action) + (multi-action 6 stmda-action) + (multi-action 5 stmda-action) + (multi-action 4 stmda-action) + (multi-action 3 stmda-action) + (multi-action 2 stmda-action) + (multi-action 1 stmda-action) + (multi-action 0 stmda-action)) +) + (dnai stmda-wb "Store multiple registers (postindex, decrement, writeback)" () "FIXME" @@ -1946,6 +2421,31 @@ (set rn addr)) ) +(dnai stmda-sw-wb "Store multiple registers (postindex, decrement, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 1) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 stmda-action-r15) + (multi-action 14 stmda-sw-action) + (multi-action 13 stmda-sw-action) + (multi-action 12 stmda-sw-action) + (multi-action 11 stmda-sw-action) + (multi-action 10 stmda-sw-action) + (multi-action 9 stmda-sw-action) + (multi-action 8 stmda-sw-action) + (multi-action 7 stmda-action) + (multi-action 6 stmda-action) + (multi-action 5 stmda-action) + (multi-action 4 stmda-action) + (multi-action 3 stmda-action) + (multi-action 2 stmda-action) + (multi-action 1 stmda-action) + (multi-action 0 stmda-action) + (set rn addr)) +) ; Coprocessor instructions. ; Currently not implemented, so omit these, such that we take the