From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16217 invoked by alias); 29 Aug 2002 10:24:21 -0000 Mailing-List: contact cgen-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sources.redhat.com Received: (qmail 16200 invoked from network); 29 Aug 2002 10:24:18 -0000 Received: from unknown (HELO www.jennic.com) (213.143.5.74) by sources.redhat.com with SMTP; 29 Aug 2002 10:24:18 -0000 Received: from jensun01.jennic.com (jensun01.jennic.com [99.99.98.151]) by www.jennic.com (8.9.3/8.9.3) with ESMTP id KAA29164; Thu, 29 Aug 2002 10:49:28 +0100 Received: from jenpc60 (jenpc60 [99.99.98.60]) by jensun01.jennic.com (8.9.3/8.9.3) with SMTP id LAA18698; Thu, 29 Aug 2002 11:24:17 +0100 (BST) From: "Robert Cragie" To: , Subject: [patch] Additional insn support for ARM7T Date: Thu, 29 Aug 2002 03:24:00 -0000 Message-ID: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0007_01C24F4E.99BDEE80" X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Importance: Normal X-SW-Source: 2002-q3/txt/msg00030.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_0007_01C24F4E.99BDEE80 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8bit Content-length: 22567 Whilst trying to get eCos to run on SID, I realised it was failing due to a LDMIA instruction not being emulated in the CPU simulator. Here is a patch to complete the combinations of LDM/STM instructions which are missing in CGEN for the ARM7. I have a feeling that it could be implemented more efficiently, but I am somewhat a newbie to Scheme, and also to contributing patches in the GNU manner, so please bear with me. I have run the testsuite by doing the following: cd build/sid/component/testsuite make check This failed, so I ran it manually: runtest --tool sidcomp --srcdir ../../../../src/sid/component/testsuite 'sidcomp.sum' is attached. Note that there are failures in the CPU monkey tests, but these also occur using the original build. I have also verified it by successfully running a program similar to the eCos 'twothreads' example. To fully update SID, the following needs to be done: cd build/sid/component/cgen-cpu/arm7t make cgen-all cd ../../../ make all install Robert Cragie, Design Engineer _______________________________________________________________ Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK http://www.jennic.com Tel: +44 (0) 114 281 2655 [src/cgen/cpu] 2002-08-29 Robert Cragie * arm7.cpu (ldm*-sw-action): New pmacros to support LDM insns * arm7.cpu (ldm*-sw-action-r15): New pmacros to support LDM insns * arm7.cpu (ldm*-sw): New LDM insn macros (PUSWL = xxSwL) * arm7.cpu (ldm*-sw-wb): New LDM insn macros (PUSWL = xxSWL) * arm7.cpu (stm*-sw-action): New pmacros to support STM insns * arm7.cpu (stm*-sw): New STM insn macros (PUSWL = xxSwl) * arm7.cpu (stm*-sw-wb): New STM insn macros (PUSWL = xxSWl) Index: cgen/cpu/arm7.cpu =================================================================== RCS file: /cvs/src/src/cgen/cpu/arm7.cpu,v retrieving revision 1.1 diff -u -p -r1.1 arm7.cpu --- cgen/cpu/arm7.cpu 5 Jul 2001 12:45:47 -0000 1.1 +++ cgen/cpu/arm7.cpu 29 Aug 2002 10:10:46 -0000 @@ -1453,6 +1453,21 @@ (set addr (sub addr 4))) ) +(define-pmacro (ldmda-sw-action bit-num) + (sequence () + (if (and reglist (sll 1 15)) + (set (reg WI h-gr bit-num) (mem WI addr)) + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr))) + (set addr (sub addr 4))) +) + +(define-pmacro (ldmda-sw-action-r15 ignored) + (sequence () + (set pc (mem WI addr)) + (set addr (sub addr 4)) + (set (reg h-cpsr) (reg h-spsr))) +) + (dnai ldmda "Load multiple registers (postindex, decrement)" () "FIXME" @@ -1479,6 +1494,32 @@ ) ) +(dnai ldmda-sw "Load multiple registers (postindex, decrement, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 0) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 ldmda-sw-action-r15) + (multi-action 14 ldmda-sw-action) + (multi-action 13 ldmda-sw-action) + (multi-action 12 ldmda-sw-action) + (multi-action 11 ldmda-sw-action) + (multi-action 10 ldmda-sw-action) + (multi-action 9 ldmda-sw-action) + (multi-action 8 ldmda-sw-action) + (multi-action 7 ldmda-action) + (multi-action 6 ldmda-action) + (multi-action 5 ldmda-action) + (multi-action 4 ldmda-action) + (multi-action 3 ldmda-action) + (multi-action 2 ldmda-action) + (multi-action 1 ldmda-action) + (multi-action 0 ldmda-action) + ) +) + (dnai ldmda-wb "Load multiple registers (postindex, decrement, writeback)" () "FIXME" @@ -1505,6 +1546,32 @@ (set rn addr)) ) +(dnai ldmda-sw-wb "Load multiple registers (postindex, decrement, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 1) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 ldmda-sw-action-r15) + (multi-action 14 ldmda-sw-action) + (multi-action 13 ldmda-sw-action) + (multi-action 12 ldmda-sw-action) + (multi-action 11 ldmda-sw-action) + (multi-action 10 ldmda-sw-action) + (multi-action 9 ldmda-sw-action) + (multi-action 8 ldmda-sw-action) + (multi-action 7 ldmda-action) + (multi-action 6 ldmda-action) + (multi-action 5 ldmda-action) + (multi-action 4 ldmda-action) + (multi-action 3 ldmda-action) + (multi-action 2 ldmda-action) + (multi-action 1 ldmda-action) + (multi-action 0 ldmda-action) + (set rn addr)) +) + (define-pmacro (ldmib-action bit-num) (sequence () (set addr (add addr 4)) @@ -1517,6 +1584,21 @@ (set pc (mem WI addr))) ) +(define-pmacro (ldmib-sw-action bit-num) + (sequence () + (set addr (add addr 4)) + (if (and reglist (sll 1 15)) + (set (reg WI h-gr bit-num) (mem WI addr)) + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr)))) +) + +(define-pmacro (ldmib-sw-action-r15 ignored) + (sequence () + (set addr (add addr 4)) + (set pc (mem WI addr)) + (set (reg h-cpsr) (reg h-spsr))) +) + (dnai ldmib "Load multiple register (preindex, increment)" () "FIXME" @@ -1542,6 +1624,31 @@ (multi-action 15 ldmib-action-r15)) ) +(dnai ldmib-sw "Load multiple register (preindex, increment, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 0) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 ldmib-action) + (multi-action 1 ldmib-action) + (multi-action 2 ldmib-action) + (multi-action 3 ldmib-action) + (multi-action 4 ldmib-action) + (multi-action 5 ldmib-action) + (multi-action 6 ldmib-action) + (multi-action 7 ldmib-action) + (multi-action 8 ldmib-sw-action) + (multi-action 9 ldmib-sw-action) + (multi-action 10 ldmib-sw-action) + (multi-action 11 ldmib-sw-action) + (multi-action 12 ldmib-sw-action) + (multi-action 13 ldmib-sw-action) + (multi-action 14 ldmib-sw-action) + (multi-action 15 ldmib-sw-action-r15)) +) + (dnai ldmib-wb "Load multiple registers (preindex, increment, writeback)" () "FIXME" @@ -1568,6 +1675,32 @@ (set rn addr)) ) +(dnai ldmib-sw-wb "Load multiple registers (preindex, increment, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 1) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 ldmib-action) + (multi-action 1 ldmib-action) + (multi-action 2 ldmib-action) + (multi-action 3 ldmib-action) + (multi-action 4 ldmib-action) + (multi-action 5 ldmib-action) + (multi-action 6 ldmib-action) + (multi-action 7 ldmib-action) + (multi-action 8 ldmib-sw-action) + (multi-action 9 ldmib-sw-action) + (multi-action 10 ldmib-sw-action) + (multi-action 11 ldmib-sw-action) + (multi-action 12 ldmib-sw-action) + (multi-action 13 ldmib-sw-action) + (multi-action 14 ldmib-sw-action) + (multi-action 15 ldmib-sw-action-r15) + (set rn addr)) +) + (define-pmacro (ldmia-action bit-num) (sequence () (set (reg WI h-gr bit-num) (mem WI addr)) @@ -1580,6 +1713,21 @@ (set addr (add addr 4))) ) +(define-pmacro (ldmia-sw-action bit-num) + (sequence () + (if (and reglist (sll 1 15)) + (set (reg WI h-gr bit-num) (mem WI addr)) + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr))) + (set addr (add addr 4))) +) + +(define-pmacro (ldmia-sw-action-r15 ignored) + (sequence () + (set pc (mem WI addr)) + (set addr (add addr 4)) + (set (reg h-cpsr) (reg h-spsr))) +) + (dnai ldmia "Load multiple registers (postindex, increment)" () "FIXME" @@ -1605,6 +1753,31 @@ (multi-action 15 ldmia-action-r15)) ) +(dnai ldmia-sw "Load multiple registers (postindex, increment, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 0) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 ldmia-action) + (multi-action 1 ldmia-action) + (multi-action 2 ldmia-action) + (multi-action 3 ldmia-action) + (multi-action 4 ldmia-action) + (multi-action 5 ldmia-action) + (multi-action 6 ldmia-action) + (multi-action 7 ldmia-action) + (multi-action 8 ldmia-sw-action) + (multi-action 9 ldmia-sw-action) + (multi-action 10 ldmia-sw-action) + (multi-action 11 ldmia-sw-action) + (multi-action 12 ldmia-sw-action) + (multi-action 13 ldmia-sw-action) + (multi-action 14 ldmia-sw-action) + (multi-action 15 ldmia-sw-action-r15)) +) + (dnai ldmia-wb "Load multiple registers (postindex, increment, writeback)" () "FIXME" @@ -1631,6 +1804,32 @@ (set rn addr)) ) +(dnai ldmia-sw-wb "Load multiple registers (postindex, increment, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 1) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 ldmia-action) + (multi-action 1 ldmia-action) + (multi-action 2 ldmia-action) + (multi-action 3 ldmia-action) + (multi-action 4 ldmia-action) + (multi-action 5 ldmia-action) + (multi-action 6 ldmia-action) + (multi-action 7 ldmia-action) + (multi-action 8 ldmia-sw-action) + (multi-action 9 ldmia-sw-action) + (multi-action 10 ldmia-sw-action) + (multi-action 11 ldmia-sw-action) + (multi-action 12 ldmia-sw-action) + (multi-action 13 ldmia-sw-action) + (multi-action 14 ldmia-sw-action) + (multi-action 15 ldmia-sw-action-r15) + (set rn addr)) +) + (define-pmacro (ldmdb-action bit-num) (sequence () (set addr (sub addr 4)) @@ -1643,6 +1842,21 @@ (set pc (mem WI addr))) ) +(define-pmacro (ldmdb-sw-action bit-num) + (sequence () + (set addr (sub addr 4)) + (if (and reglist (sll 1 15)) + (set (reg WI h-gr bit-num) (mem WI addr)) + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr)))) +) + +(define-pmacro (ldmdb-sw-action-r15 ignored) + (sequence () + (set addr (sub addr 4)) + (set pc (mem WI addr)) + (set (reg h-cpsr) (reg h-spsr))) +) + (dnai ldmdb "Load multiple registers (preindex, decrement)" () "ldm$cond .." @@ -1668,6 +1882,31 @@ (multi-action 0 ldmdb-action)) ) +(dnai ldmdb-sw "Load multiple registers (preindex, decrement, switch)" + () + "ldm$cond .." + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 0) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 ldmdb-sw-action-r15) + (multi-action 14 ldmdb-sw-action) + (multi-action 13 ldmdb-sw-action) + (multi-action 12 ldmdb-sw-action) + (multi-action 11 ldmdb-sw-action) + (multi-action 10 ldmdb-sw-action) + (multi-action 9 ldmdb-sw-action) + (multi-action 8 ldmdb-sw-action) + (multi-action 7 ldmdb-action) + (multi-action 6 ldmdb-action) + (multi-action 5 ldmdb-action) + (multi-action 4 ldmdb-action) + (multi-action 3 ldmdb-action) + (multi-action 2 ldmdb-action) + (multi-action 1 ldmdb-action) + (multi-action 0 ldmdb-action)) +) + (dnai ldmdb-wb "Load multiple registers (preindex, decrement, writeback)" () "FIXME" @@ -1694,12 +1933,46 @@ (set rn addr)) ) +(dnai ldmdb-sw-wb "Load multiple registers (preindex, decrement, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 1) (f-load? 1) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 ldmdb-sw-action-r15) + (multi-action 14 ldmdb-sw-action) + (multi-action 13 ldmdb-sw-action) + (multi-action 12 ldmdb-sw-action) + (multi-action 11 ldmdb-sw-action) + (multi-action 10 ldmdb-sw-action) + (multi-action 9 ldmdb-sw-action) + (multi-action 8 ldmdb-sw-action) + (multi-action 7 ldmdb-action) + (multi-action 6 ldmdb-action) + (multi-action 5 ldmdb-action) + (multi-action 4 ldmdb-action) + (multi-action 3 ldmdb-action) + (multi-action 2 ldmdb-action) + (multi-action 1 ldmdb-action) + (multi-action 0 ldmdb-action) + (set rn addr)) +) + (define-pmacro (stmdb-action bit-num) (sequence () (set addr (sub addr 4)) (set (mem WI addr) (reg WI h-gr bit-num))) ) +(define-pmacro (stmdb-sw-action bit-num) + (sequence () + (set addr (sub addr 4)) + (if (and reglist (sll 1 15)) + (set (mem WI addr) (reg WI h-gr bit-num)) + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8))))) +) + (define-pmacro (stmdb-action-r15 ignore) (sequence () (set addr (sub addr 4)) @@ -1731,6 +2004,31 @@ (multi-action 0 stmdb-action)) ) +(dnai stmdb-sw "Store multiple registers (preindex, decrement, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 0) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 stmdb-action-r15) + (multi-action 14 stmdb-sw-action) + (multi-action 13 stmdb-sw-action) + (multi-action 12 stmdb-sw-action) + (multi-action 11 stmdb-sw-action) + (multi-action 10 stmdb-sw-action) + (multi-action 9 stmdb-sw-action) + (multi-action 8 stmdb-sw-action) + (multi-action 7 stmdb-action) + (multi-action 6 stmdb-action) + (multi-action 5 stmdb-action) + (multi-action 4 stmdb-action) + (multi-action 3 stmdb-action) + (multi-action 2 stmdb-action) + (multi-action 1 stmdb-action) + (multi-action 0 stmdb-action)) +) + (dnai stmdb-wb "Store multiple registers (preindex, decrement, writeback)" () "FIXME" @@ -1757,12 +2055,46 @@ (set rn addr)) ) +(dnai stmdb-sw-wb "Store multiple registers (preindex, decrement, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 1) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 stmdb-action-r15) + (multi-action 14 stmdb-sw-action) + (multi-action 13 stmdb-sw-action) + (multi-action 12 stmdb-sw-action) + (multi-action 11 stmdb-sw-action) + (multi-action 10 stmdb-sw-action) + (multi-action 9 stmdb-sw-action) + (multi-action 8 stmdb-sw-action) + (multi-action 7 stmdb-action) + (multi-action 6 stmdb-action) + (multi-action 5 stmdb-action) + (multi-action 4 stmdb-action) + (multi-action 3 stmdb-action) + (multi-action 2 stmdb-action) + (multi-action 1 stmdb-action) + (multi-action 0 stmdb-action) + (set rn addr)) +) + (define-pmacro (stmib-action bit-num) (sequence () (set addr (add addr 4)) (set (mem WI addr) (reg WI h-gr bit-num))) ) +(define-pmacro (stmib-sw-action bit-num) + (sequence () + (set addr (add addr 4)) + (if (and reglist (sll 1 15)) + (set (mem WI addr) (reg WI h-gr bit-num)) + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8))))) +) + (define-pmacro (stmib-action-r15 ignore) (sequence () (set addr (add addr 4)) @@ -1794,6 +2126,31 @@ (multi-action 15 stmib-action-r15)) ) +(dnai stmib-sw "Store multiple registers (preindex, increment, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 0) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 stmib-action) + (multi-action 1 stmib-action) + (multi-action 2 stmib-action) + (multi-action 3 stmib-action) + (multi-action 4 stmib-action) + (multi-action 5 stmib-action) + (multi-action 6 stmib-action) + (multi-action 7 stmib-action) + (multi-action 8 stmib-sw-action) + (multi-action 9 stmib-sw-action) + (multi-action 10 stmib-sw-action) + (multi-action 11 stmib-sw-action) + (multi-action 12 stmib-sw-action) + (multi-action 13 stmib-sw-action) + (multi-action 14 stmib-sw-action) + (multi-action 15 stmib-action-r15)) +) + (dnai stmib-wb "Store multiple registers (preindex, increment, writeback)" () "FIXME" @@ -1820,12 +2177,46 @@ (set rn addr)) ) +(dnai stmib-sw-wb "Store multiple registers (preindex, increment, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 1) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 stmib-action) + (multi-action 1 stmib-action) + (multi-action 2 stmib-action) + (multi-action 3 stmib-action) + (multi-action 4 stmib-action) + (multi-action 5 stmib-action) + (multi-action 6 stmib-action) + (multi-action 7 stmib-action) + (multi-action 8 stmib-sw-action) + (multi-action 9 stmib-sw-action) + (multi-action 10 stmib-sw-action) + (multi-action 11 stmib-sw-action) + (multi-action 12 stmib-sw-action) + (multi-action 13 stmib-sw-action) + (multi-action 14 stmib-sw-action) + (multi-action 15 stmib-action-r15) + (set rn addr)) +) + (define-pmacro (stmia-action bit-num) (sequence () (set (mem WI addr) (reg WI h-gr bit-num)) (set addr (add addr 4))) ) +(define-pmacro (stmia-sw-action bit-num) + (sequence () + (if (and reglist (sll 1 15)) + (set (mem WI addr) (reg WI h-gr bit-num)) + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8)))) + (set addr (add addr 4))) +) + (define-pmacro (stmia-action-r15 ignore) (sequence () (set (mem WI addr) (add (reg WI h-gr 15) 4)) @@ -1857,6 +2248,31 @@ (multi-action 15 stmia-action-r15)) ) +(dnai stmia-sw "Store multiple registers (postindex, increment, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 0) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 stmia-action) + (multi-action 1 stmia-action) + (multi-action 2 stmia-action) + (multi-action 3 stmia-action) + (multi-action 4 stmia-action) + (multi-action 5 stmia-action) + (multi-action 6 stmia-action) + (multi-action 7 stmia-action) + (multi-action 8 stmia-sw-action) + (multi-action 9 stmia-sw-action) + (multi-action 10 stmia-sw-action) + (multi-action 11 stmia-sw-action) + (multi-action 12 stmia-sw-action) + (multi-action 13 stmia-sw-action) + (multi-action 14 stmia-sw-action) + (multi-action 15 stmia-action-r15)) +) + (dnai stmia-wb "Store multiple registers (postindex, increment, writeback)" () "FIXME" @@ -1883,12 +2299,46 @@ (set rn addr)) ) +(dnai stmia-sw-wb "Store multiple registers (postindex, increment, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1) + (f-write-back? 1) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 0 stmia-action) + (multi-action 1 stmia-action) + (multi-action 2 stmia-action) + (multi-action 3 stmia-action) + (multi-action 4 stmia-action) + (multi-action 5 stmia-action) + (multi-action 6 stmia-action) + (multi-action 7 stmia-action) + (multi-action 8 stmia-sw-action) + (multi-action 9 stmia-sw-action) + (multi-action 10 stmia-sw-action) + (multi-action 11 stmia-sw-action) + (multi-action 12 stmia-sw-action) + (multi-action 13 stmia-sw-action) + (multi-action 14 stmia-sw-action) + (multi-action 15 stmia-action-r15) + (set rn addr)) +) + (define-pmacro (stmda-action-r15 ignore) (sequence () (set (mem WI addr) (add (reg WI h-gr 15) 4)) (set addr (sub addr 4))) ) +(define-pmacro (stmda-sw-action bit-num) + (sequence () + (if (and reglist (sll 1 15)) + (set (mem WI addr) (reg WI h-gr bit-num)) + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8)))) + (set addr (sub addr 4))) +) + (define-pmacro (stmda-action bit-num) (sequence () (set (mem WI addr) (reg WI h-gr bit-num)) @@ -1920,6 +2370,31 @@ (multi-action 0 stmda-action)) ) +(dnai stmda-sw "Store multiple registers (postindex, decrement, switch)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 0) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 stmda-action-r15) + (multi-action 14 stmda-sw-action) + (multi-action 13 stmda-sw-action) + (multi-action 12 stmda-sw-action) + (multi-action 11 stmda-sw-action) + (multi-action 10 stmda-sw-action) + (multi-action 9 stmda-sw-action) + (multi-action 8 stmda-sw-action) + (multi-action 7 stmda-action) + (multi-action 6 stmda-action) + (multi-action 5 stmda-action) + (multi-action 4 stmda-action) + (multi-action 3 stmda-action) + (multi-action 2 stmda-action) + (multi-action 1 stmda-action) + (multi-action 0 stmda-action)) +) + (dnai stmda-wb "Store multiple registers (postindex, decrement, writeback)" () "FIXME" @@ -1946,6 +2421,31 @@ (set rn addr)) ) +(dnai stmda-sw-wb "Store multiple registers (postindex, decrement, switch, writeback)" + () + "FIXME" + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1) + (f-write-back? 1) (f-load? 0) rn reglist) + (sequence ((WI addr)) + (set addr rn) + (multi-action 15 stmda-action-r15) + (multi-action 14 stmda-sw-action) + (multi-action 13 stmda-sw-action) + (multi-action 12 stmda-sw-action) + (multi-action 11 stmda-sw-action) + (multi-action 10 stmda-sw-action) + (multi-action 9 stmda-sw-action) + (multi-action 8 stmda-sw-action) + (multi-action 7 stmda-action) + (multi-action 6 stmda-action) + (multi-action 5 stmda-action) + (multi-action 4 stmda-action) + (multi-action 3 stmda-action) + (multi-action 2 stmda-action) + (multi-action 1 stmda-action) + (multi-action 0 stmda-action) + (set rn addr)) +) ; Coprocessor instructions. ; Currently not implemented, so omit these, such that we take the ------=_NextPart_000_0007_01C24F4E.99BDEE80 Content-Type: application/octet-stream; name="sidcomp.sum" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="sidcomp.sum" Content-length: 117137 Test Run By rcc on Wed Aug 28 16:02:51 2002=0A= Native configuration is i686-pc-linux-gnu=0A= =0A= =3D=3D=3D sidcomp tests =3D=3D=3D=0A= =0A= Schedule of variations:=0A= unix=0A= =0A= Running target unix=0A= Running ../../../../src/sid/component/testsuite/sidcomp.audio/aumonkey.exp = ...=0A= PASS: monkey test sid-io-audio (30s iterations)=0A= PASS: monkey test hw-audio-sid (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.audio/linuscodec.ex= p ...=0A= UNTESTED: arm7 linuscodec.c (,,-O2 -DSIDCODEC=3D0xE0000000 -mbig-endian,--c= pu=3Darm --sidcodec=3D0xE0000000) - compile failed=0A= Running ../../../../src/sid/component/testsuite/sidcomp.audio/linusraw.exp = ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: load Linus sound sample from ../../../../src/sid/component/testsuite/= sidcomp.audio/linusraw.bin=0A= PASS: set configuration=0A= FAIL: assert tx=0A= PASS: play Linus sound sample=0A= PASS: poll until tx buf drained=0A= FAIL: deassert tx=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.bsp/armbsp.exp ...= =0A= UNTESTED: arm7 test-insn.c (,,-g -O2 -mlittle-endian,--cpu=3Darm --engine= =3Dscache) - compile failed=0A= UNTESTED: arm7 test-memory.c (,,-g -O2 -mlittle-endian,--cpu=3Darm --engine= =3Dscache) - compile failed=0A= UNTESTED: arm7 test-insn.c (,,-g -O2 -mbig-endian,--cpu=3Darm --engine=3Dsc= ache) - compile failed=0A= UNTESTED: arm7 test-memory.c (,,-g -O2 -mbig-endian,--cpu=3Darm --engine=3D= scache) - compile failed=0A= UNTESTED: arm7 test-insn.c (,,-g -O2 -mlittle-endian,--cpu=3Darm --engine= =3Dpbb) - compile failed=0A= UNTESTED: arm7 test-memory.c (,,-g -O2 -mlittle-endian,--cpu=3Darm --engine= =3Dpbb) - compile failed=0A= UNTESTED: arm7 test-insn.c (,,-g -O2 -mbig-endian,--cpu=3Darm --engine=3Dpb= b) - compile failed=0A= UNTESTED: arm7 test-memory.c (,,-g -O2 -mbig-endian,--cpu=3Darm --engine=3D= pbb) - compile failed=0A= UNTESTED: arm7t test-insn.c (,,-g -O2 -mlittle-endian -mthumb -mthumb-inter= work,--cpu=3Dthumb --engine=3Dscache) - compile failed=0A= UNTESTED: arm7t test-memory.c (,,-g -O2 -mlittle-endian -mthumb -mthumb-int= erwork,--cpu=3Dthumb --engine=3Dscache) - compile failed=0A= UNTESTED: arm7t test-insn.c (,,-g -O2 -mbig-endian -mthumb -mthumb-interwor= k,--cpu=3Dthumb --engine=3Dscache) - compile failed=0A= UNTESTED: arm7t test-memory.c (,,-g -O2 -mbig-endian -mthumb -mthumb-interw= ork,--cpu=3Dthumb --engine=3Dscache) - compile failed=0A= UNTESTED: arm7t test-insn.c (,,-g -O2 -mlittle-endian -mthumb -mthumb-inter= work,--cpu=3Dthumb --engine=3Dpbb) - compile failed=0A= UNTESTED: arm7t test-memory.c (,,-g -O2 -mlittle-endian -mthumb -mthumb-int= erwork,--cpu=3Dthumb --engine=3Dpbb) - compile failed=0A= UNTESTED: arm7t test-insn.c (,,-g -O2 -mbig-endian -mthumb -mthumb-interwor= k,--cpu=3Dthumb --engine=3Dpbb) - compile failed=0A= UNTESTED: arm7t test-memory.c (,,-g -O2 -mbig-endian -mthumb -mthumb-interw= ork,--cpu=3Dthumb --engine=3Dpbb) - compile failed=0A= Running ../../../../src/sid/component/testsuite/sidcomp.bsp/dhrystone.exp .= ..=0A= UNTESTED: arm7 dhry21.c (,,-g -O2 -DSID=3D0xE0000000 -mbig-endian,--cpu=3Da= rm --sidrtc=3D0xE0000000) - compile failed=0A= UNTESTED: arm7 dhry21.c (,,-g -O2 -DSID=3D0xE0000000 -mlittle-endian,--cpu= =3Darm --sidrtc=3D0xE0000000) - compile failed=0A= UNTESTED: arm7t dhry21.c (,,-g -O2 -DSID=3D0xE0000000 -mbig-endian -mthumb = -mthumb-interwork,--cpu=3Dthumb --sidrtc=3D0xE0000000) - compile failed=0A= UNTESTED: arm7t dhry21.c (,,-g -O2 -DSID=3D0xE0000000 -mlittle-endian -mthu= mb -mthumb-interwork,--cpu=3Dthumb --sidrtc=3D0xE0000000) - compile failed= =0A= Running ../../../../src/sid/component/testsuite/sidcomp.bsp/m32rbsp.exp ...= =0A= UNTESTED: m32r test-insn.c (,,-g -O2,--cpu=3Dm32r) - compile failed=0A= UNTESTED: m32r test-memory.c (,,-g -O2,--cpu=3Dm32r) - compile failed=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/cache.exp ...= =0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: all pins are present=0A= PASS: all attributes are present=0A= PASS: upstream bus is present=0A= PASS: downstream accessor is present=0A= PASS: read-accesses initialised to 0=0A= PASS: write-accesses initialised to 0=0A= PASS: misaligned-reads initialised to 0=0A= PASS: misaligned-writes initialised to 0=0A= PASS: flushes initialised to 0=0A= PASS: replacements initialised to 0=0A= PASS: read-hit-rate is initialised to 0%=0A= PASS: write-hit-rate is initialised to 0%=0A= PASS: associativity is set for hw-cache-basic=0A= PASS: cache-size is set for hw-cache-basic=0A= PASS: line-size is set for hw-cache-basic=0A= PASS: write-through? is set for hw-cache-basic=0A= PASS: write-allocate? is set for hw-cache-basic=0A= PASS: collect-statistics? is set for hw-cache-basic=0A= PASS: report-heading is set for hw-cache-basic=0A= PASS: acquire upstream bus handle=0A= PASS: generate test bus for downstream=0A= PASS: connect test bus to cache=0A= PASS: read a byte from 0x100 (miss)=0A= PASS: read-accesses attribute has been incremented=0A= PASS: read a byte from 0x100 (hit)=0A= PASS: read-accesses attribute has been incremented=0A= PASS: read another byte on the same line as 0x100 (hit)=0A= PASS: read-accesses attribute has been incremented=0A= PASS: read from 0x4100 which hashes to the same line (miss)=0A= PASS: read-accesses attribute has been incremented=0A= PASS: replacements attribute has been incremented=0A= PASS: flushes attribute is invariant=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/cachedocs.exp= ...=0A= PASS: Documentation file (txt) for hw-cache-basic exists=0A= PASS: Documentation file (xml) for hw-cache-basic exists=0A= PASS: Documentation file seems to document hw-cache-basic=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/cachemonkey.e= xp ...=0A= PASS: monkey test hw-cache-2way/256kb/16/fifo (30s iterations)=0A= PASS: monkey test hw-cache-basic (30s iterations)=0A= PASS: monkey test hw-cache-4way/8kb/64/lru (30s iterations)=0A= PASS: monkey test hw-cache-full/64kb/32/random (30s iterations)=0A= PASS: monkey test hw-cache-direct/16kb/128 (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/coherency.exp= ...=0A= PASS: sid startup=0A= PASS: acquire upstream bus handle=0A= PASS: cache coherency=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/fifo.exp ...= =0A= PASS: sid startup=0A= PASS: acquire upstream bus handle=0A= PASS: generate test bus for downstream=0A= PASS: connect test bus to cache=0A= PASS: read byte from 0x100 (miss)=0A= PASS: read byte from 0x4100 (miss)=0A= PASS: read byte from 0x8100 (miss)=0A= PASS: read byte from 0xc100 (miss)=0A= PASS: read byte again from 0x100 (hit)=0A= PASS: read byte again from 0x4100 (hit)=0A= PASS: read byte again from 0x8100 (hit)=0A= PASS: read byte again from 0xc100 (hit)=0A= PASS: read byte from 0x10100 (miss)=0A= PASS: line for 0x8100 is still in the cache (hit)=0A= PASS: line for 0x100 has been removed from the cache (miss)=0A= PASS: line for 0x8100 is still in the cache (hit)=0A= PASS: read byte from 0x14100 (miss)=0A= PASS: line for 0x8100 has been removed from the cache (miss)=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/flush.exp ...= =0A= PASS: sid startup=0A= PASS: acquire upstream bus handle=0A= PASS: generate test bus for downstream=0A= PASS: connect test bus to cache=0A= PASS: read a byte from 0x100 (miss)=0A= PASS: write a byte to 0x100 (hit)=0A= PASS: flush dirty line (miss)=0A= PASS: flush clean line (hit)=0A= PASS: read a line (miss)=0A= PASS: make a line dirty (hit)=0A= PASS: displacing a dirty line causes bus activity (miss)=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/lock.exp ...= =0A= PASS: sid startup=0A= PASS: acquire upstream bus handle=0A= PASS: generate test bus for downstream=0A= PASS: connect test bus to cache=0A= PASS: read a byte from 0x100 (miss)=0A= PASS: read another byte from 0x100 (hit)=0A= PASS: lock 0x100=0A= PASS: double lock=0A= PASS: read a byte from 0x100 (hit)=0A= PASS: read a byte from 0x4100 (miss)=0A= PASS: read another byte from 0x4100 (miss)=0A= PASS: read a byte from 0x100 (hit)=0A= PASS: unlock 0x100=0A= PASS: double unlock=0A= PASS: read a byte from 0x4100 (miss)=0A= PASS: read another byte from 0x4100 (hit)=0A= PASS: replacements stat equals 2=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/lru.exp ...= =0A= PASS: sid startup=0A= PASS: acquire upstream bus handle=0A= PASS: generate test bus for downstream=0A= PASS: connect test bus to cache=0A= PASS: read byte from 0x100 (miss)=0A= PASS: read byte from 0x4100 (miss)=0A= PASS: read byte from 0x8100 (miss)=0A= PASS: read byte from 0xc100 (miss)=0A= PASS: read byte again from 0x100 (hit)=0A= PASS: read byte again from 0x4100 (hit)=0A= PASS: read byte again from 0x8100 (hit)=0A= PASS: read byte again from 0xc100 (hit)=0A= PASS: read byte from 0x10100 (miss)=0A= PASS: read byte from 0x8100 (hit)=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/misaligned.ex= p ...=0A= PASS: sid startup=0A= PASS: acquire upstream bus handle=0A= PASS: generate test bus for downstream=0A= PASS: connect test bus to cache=0A= PASS: misaligned read from 0x101 (miss)=0A= PASS: read-accesses attribute has been incremented=0A= PASS: misaligned-reads attribute has been incremented=0A= PASS: write-accesses attribute is invariant=0A= PASS: misaligned-writes attribute is invariant=0A= PASS: misaligned write to 0x105 (miss)=0A= PASS: write-accesses attribute has been incremented=0A= PASS: misaligned-writes attribute has been incremented=0A= PASS: read-accesses attribute is invariant=0A= PASS: misaligned-reads attribute is invariant=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/prefetch.exp = ...=0A= PASS: sid startup=0A= PASS: acquire upstream bus handle=0A= PASS: generate test bus for downstream=0A= PASS: connect test bus to cache=0A= PASS: connect test bus to cache=0A= PASS: read a byte from 0x100 (hit)=0A= PASS: read a byte from 0x4100 (miss)=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/random.exp ..= .=0A= PASS: sid startup=0A= PASS: acquire upstream bus handle=0A= PASS: generate test bus for downstream=0A= PASS: connect test bus to cache=0A= PASS: read byte from 0x100 (miss)=0A= PASS: read byte from 0x4100 (miss)=0A= PASS: read byte from 0x8100 (miss)=0A= PASS: read byte from 0xc100 (miss)=0A= PASS: read byte again from 0x100 (hit)=0A= PASS: read byte again from 0x4100 (hit)=0A= PASS: read byte again from 0x8100 (hit)=0A= PASS: read byte again from 0xc100 (hit)=0A= PASS: read byte from 0x10100 (miss)=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/refill.exp ..= .=0A= PASS: sid startup=0A= PASS: acquire upstream bus handle=0A= PASS: generate test bus for downstream=0A= PASS: connect test bus to cache=0A= PASS: read from 0x100 (miss)=0A= PASS: read from 0x1000 (use miss latency)=0A= PASS: read from 0x100 (miss)=0A= PASS: read from 0x1000 (use refill latency)=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/utils.exp ...= =0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/writealloc.ex= p ...=0A= PASS: sid startup=0A= PASS: acquire upstream bus handle=0A= PASS: generate test bus for downstream=0A= PASS: connect test bus to cache=0A= PASS: write byte to 0x100 (miss)=0A= PASS: read byte from 0x100 (hit)=0A= PASS: another write to 0x100 (hit)=0A= PASS: another read from 0x100 (hit)=0A= PASS: write byte to 0x500 (miss)=0A= PASS: read byte from 0x500 (miss)=0A= PASS: read byte from 0x500 again (hit)=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cache/writethru.exp= ...=0A= PASS: sid startup=0A= PASS: acquire upstream bus handle=0A= PASS: generate test bus for downstream=0A= PASS: connect test bus to cache=0A= PASS: read byte from 0x100 (miss)=0A= PASS: read byte from 0x100 (hit)=0A= PASS: write byte to 0x100 (miss)=0A= PASS: read byte back from 0x100 (hit)=0A= PASS: read byte from 0x500 (miss)=0A= PASS: read byte from 0x500 (hit)=0A= PASS: write byte to 0x500 (hit)=0A= PASS: read byte back from 0x500 (hit)=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cfgroot/badconf.exp= ...=0A= PASS: handle bad configuration file (CBinvaComp.badconf)=0A= PASS: handle bad configuration file (CBinvaName.badconf)=0A= PASS: handle bad configuration file (CPinvaComp.badconf)=0A= PASS: handle bad configuration file (CPinvaPin.badconf)=0A= PASS: handle bad configuration file (comment.badconf)=0A= PASS: handle bad configuration file (cr100925.badconf)=0A= PASS: handle bad configuration file (cr100931.badconf)=0A= PASS: handle bad configuration file (cr100942.badconf)=0A= PASS: handle bad configuration file (dupName.badconf)=0A= PASS: handle bad configuration file (dupRel.badconf)=0A= PASS: handle bad configuration file (empty.badconf)=0A= PASS: handle bad configuration file (extMiss.badconf)=0A= PASS: handle bad configuration file (illegCh.badconf)=0A= PASS: handle bad configuration file (invaComp.badconf)=0A= PASS: handle bad configuration file (invaName.badconf)=0A= PASS: handle bad configuration file (invaRel.badconf)=0A= PASS: handle bad configuration file (libErr.badconf)=0A= PASS: handle bad configuration file (multiCB.badconf)=0A= PASS: handle bad configuration file (multiCP.badconf)=0A= PASS: handle bad configuration file (multiDso.badconf)=0A= PASS: handle bad configuration file (multiSet.badconf)=0A= PASS: handle bad configuration file (setInvAtt.badconf)=0A= PASS: handle bad configuration file (setInvAttV.badconf)=0A= PASS: handle bad configuration file (setInvComp.badconf)=0A= PASS: handle bad configuration file (symErr.badconf)=0A= PASS: handle bad configuration file (unknown.badconf)=0A= PASS: handle bad configuration file (wrongOrd.badconf)=0A= PASS: handle bad configuration file (wrongOrd1.badconf)=0A= PASS: handle bad configuration file (wrongOrd2.badconf)=0A= PASS: handle bad configuration file (wrongOrd3.badconf)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cfgroot/cfgrootdocs= .exp ...=0A= PASS: Documentation file (txt) for sid-control-cfgroot exists=0A= PASS: Documentation file (xml) for sid-control-cfgroot exists=0A= PASS: Documentation file seems to document sid-control-cfgroot=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cgen-cpu/cpudocs.ex= p ...=0A= PASS: Documentation file (txt) for hw-cpu-arm7t exists=0A= FAIL: Documentation file (xml) for hw-cpu-arm7t is missing=0A= FAIL: Documentation file does not seem to document hw-cpu-arm7t=0A= PASS: Documentation file (txt) for hw-cpu-m32r/d exists=0A= FAIL: Documentation file (xml) for hw-cpu-m32r/d is missing=0A= FAIL: Documentation file does not seem to document hw-cpu-m32r/d=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cgen-cpu/cpumonkey.= exp ...=0A= NOTE: Testing hw-cpu-arm7t until Wed Aug 28 16:09:54 BST 2002=0A= WARNING: monkey test hw-cpu-arm7t - state restore failed=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve pc=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve gdb-regi= ster-pc=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve trace-fi= lename=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r10=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r11_fiq= =0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r12=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r14_abt= =0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r15=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve cpsr=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve cpsr-fla= gs=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve spsr_abt= =0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r6=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r14=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r4=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r1=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve spsr_und= =0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r14_und= =0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r7=0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r13_fiq= =0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve spsr_svc= =0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve spsr_irq= =0A= WARNING: monkey test hw-cpu-arm7t - state restore did not preserve r11=0A= UNRESOLVED: monkey test hw-cpu-arm7t (3m iterations)=0A= WARNING: monkey test hw-cpu-m32r/d - state restore failed=0A= WARNING: monkey test hw-cpu-m32r/d - state restore did not preserve r0=0A= WARNING: monkey test hw-cpu-m32r/d - state restore did not preserve r10=0A= WARNING: monkey test hw-cpu-m32r/d - state restore did not preserve r14=0A= WARNING: monkey test hw-cpu-m32r/d - state restore did not preserve pc=0A= WARNING: monkey test hw-cpu-m32r/d - state restore did not preserve gdb-reg= ister-pc=0A= WARNING: monkey test hw-cpu-m32r/d - state restore did not preserve trace-f= ilename=0A= WARNING: monkey test hw-cpu-m32r/d - state restore did not preserve r1=0A= WARNING: monkey test hw-cpu-m32r/d - state restore did not preserve r4=0A= WARNING: monkey test hw-cpu-m32r/d - state restore did not preserve r7=0A= WARNING: monkey test hw-cpu-m32r/d - state restore did not preserve r12=0A= UNRESOLVED: monkey test hw-cpu-m32r/d (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cgen-cpu.arm7t/armc= onf.exp ...=0A= FAIL: arm7tdmi armfiq.cs (-EL,-EL,,) #0=0A= FAIL: arm7tdmi armirq.cs (-EL,-EL,,) #0=0A= FAIL: arm7tdmi armfiq.cs (-EB,-EB,,) #0=0A= FAIL: arm7tdmi armirq.cs (-EB,-EB,,) #0=0A= Running ../../../../src/sid/component/testsuite/sidcomp.cgen-cpu.arm7t/armm= isc.exp ...=0A= PASS: arm7tdmi armhello.ms (-EL,-EL,,--cpu=3Darm --engine=3Dscache) #0=0A= PASS: arm7tdmi armimemfault.ms (-EL,-EL,,--cpu=3Darm --engine=3Dscache) #0= =0A= FAIL: arm7tdmi arminvinsn.ms (-EL,-EL,,--cpu=3Darm --engine=3Dscache) #0=0A= PASS: arm7tdmi armmemfault.ms (-EL,-EL,,--cpu=3Darm --engine=3Dscache) #0= =0A= PASS: arm7tdmi armhello.ms (-EB,-EB,,--cpu=3Darm --engine=3Dscache) #0=0A= PASS: arm7tdmi armimemfault.ms (-EB,-EB,,--cpu=3Darm --engine=3Dscache) #0= =0A= FAIL: arm7tdmi arminvinsn.ms (-EB,-EB,,--cpu=3Darm --engine=3Dscache) #0=0A= PASS: arm7tdmi armmemfault.ms (-EB,-EB,,--cpu=3Darm --engine=3Dscache) #0= =0A= Running ../../../../src/sid/component/testsuite/sidcomp.cgen-cpu.xstormy16/= xstormy16-allinsn.exp ...=0A= UNTESTED: xstormy16 adcgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 adcgrimm16.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 adcgrimm4.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 adcimm8.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 addgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 addgrimm16.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 addgrimm4.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 addimm8.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 andgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 andgrimm16.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 andimm8.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 asrgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 asrgrimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 bcc.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 bccgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 bccgrimm8.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 bccimm16.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 bgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 bngrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 bngrimm4.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 bnhmemimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 bnlmemimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 bpgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 bpgrimm4.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 bphmemimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 bplmemimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 callfimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 callgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 callrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 callrimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 cbwgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 clr1grgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 clr1grimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 clr1hmemimm.cgs (,,,--cpu=3Dxstormy16) - assembly faile= d=0A= UNTESTED: xstormy16 clr1lmemimm.cgs (,,,--cpu=3Dxstormy16) - assembly faile= d=0A= UNTESTED: xstormy16 decgrimm2.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 div.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 icallfimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 icallgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 icallrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 incgrimm2.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 jmp.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 jmpf.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 maskgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 maskgrimm16.cgs (,,,--cpu=3Dxstormy16) - assembly faile= d=0A= UNTESTED: xstormy16 movgrgri.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 movgrgrii.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 movgrgriipostinc.cgs (,,,--cpu=3Dxstormy16) - assembly = failed=0A= UNTESTED: xstormy16 movgrgriipredec.cgs (,,,--cpu=3Dxstormy16) - assembly f= ailed=0A= UNTESTED: xstormy16 movgrgripostinc.cgs (,,,--cpu=3Dxstormy16) - assembly f= ailed=0A= UNTESTED: xstormy16 movgrgripredec.cgs (,,,--cpu=3Dxstormy16) - assembly fa= iled=0A= UNTESTED: xstormy16 movgrigr.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 movgriigr.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 movgriipostincgr.cgs (,,,--cpu=3Dxstormy16) - assembly = failed=0A= UNTESTED: xstormy16 movgriipredecgr.cgs (,,,--cpu=3Dxstormy16) - assembly f= ailed=0A= UNTESTED: xstormy16 movgripostincgr.cgs (,,,--cpu=3Dxstormy16) - assembly f= ailed=0A= UNTESTED: xstormy16 movgripredecgr.cgs (,,,--cpu=3Dxstormy16) - assembly fa= iled=0A= UNTESTED: xstormy16 movhgrmem.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 movhighgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 movlgrmem.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 movlmemgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 movlmemimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 movlowgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 mul.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 notgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 orgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 orgrimm16.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 orimm8.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 pushpop.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 revgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 rlcgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 rlcgrimm4.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 rrcgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 rrcgrimm4.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 sbcgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 sbcgrimm16.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 sbcgrimm4.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 sbcgrimm8.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 set1grgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 set1grimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 set1hmemimm.cgs (,,,--cpu=3Dxstormy16) - assembly faile= d=0A= UNTESTED: xstormy16 set1lmemimm.cgs (,,,--cpu=3Dxstormy16) - assembly faile= d=0A= UNTESTED: xstormy16 shlgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 shlgrimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 shrgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 shrgrimm.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 subgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 subgrimm16.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 subgrimm4.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 subimm8.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 swap.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 xorgrgr.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= UNTESTED: xstormy16 xorgrimm16.cgs (,,,--cpu=3Dxstormy16) - assembly failed= =0A= UNTESTED: xstormy16 xorimm8.cgs (,,,--cpu=3Dxstormy16) - assembly failed=0A= Running ../../../../src/sid/component/testsuite/sidcomp.consoles/consdocs.e= xp ...=0A= PASS: Documentation file (txt) for sid-io-stdio exists=0A= PASS: Documentation file (xml) for sid-io-stdio exists=0A= PASS: Documentation file seems to document sid-io-stdio=0A= PASS: Documentation file (txt) for sid-io-socket-server exists=0A= PASS: Documentation file (xml) for sid-io-socket-server exists=0A= PASS: Documentation file seems to document sid-io-socket-server=0A= Running ../../../../src/sid/component/testsuite/sidcomp.consoles/consmonkey= .exp ...=0A= Running ../../../../src/sid/component/testsuite/sidcomp.consoles/socketinv.= exp ...=0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: find pin that does not exist=0A= PASS: connect to a pin that does not exist=0A= PASS: check connected pins on a pin that does not exist=0A= PASS: check disconnecting pin on a pin that does not exist=0A= PASS: find bus that does not exist=0A= PASS: connect to an accessor that does not exist=0A= PASS: check connected bus on a bus that does not exist=0A= PASS: set relationships that does not exist=0A= PASS: set relationships to relate to a non existing component=0A= PASS: query relationships that does not exist=0A= PASS: set non existing attribute to -1=0A= PASS: set attribute tx-count to -1=0A= PASS: set attribute tx-count to 127.0.0.0:xxx=0A= PASS: set attribute tx-count to true=0A= PASS: set attribute tx-count to 0.0e0=0A= PASS: set attribute rx-count to -1=0A= PASS: set attribute rx-count to 127.0.0.0:xxx=0A= PASS: set attribute rx-count to true=0A= PASS: set attribute rx-count to 0.0e0=0A= PASS: set attribute poll-count to -1=0A= PASS: set attribute poll-count to 127.0.0.0:xxx=0A= PASS: set attribute poll-count to true=0A= PASS: set attribute poll-count to 0.0e0=0A= PASS: set attribute max-poll-interval to -1=0A= PASS: set attribute max-poll-interval to 127.0.0.0:xxx=0A= PASS: set attribute max-poll-interval to true=0A= PASS: set attribute max-poll-interval to 0.0e0=0A= PASS: set attribute poll-interval to -1=0A= PASS: set attribute poll-interval to 127.0.0.0:xxx=0A= PASS: set attribute poll-interval to true=0A= PASS: set attribute poll-interval to 0.0e0=0A= PASS: set attribute server? to -1=0A= PASS: set attribute server? to 127.0.0.0:xxx=0A= PASS: set attribute server? to 123e5=0A= PASS: set attribute server? to string=0A= PASS: set attribute verbose? to -1=0A= PASS: set attribute verbose? to 127.0.0.0:xxx=0A= PASS: set attribute verbose? to 123e5=0A= PASS: set attribute verbose? to string=0A= PASS: set attribute trace-traffic? to -1=0A= PASS: set attribute trace-traffic? to 127.0.0.0:xxx=0A= PASS: set attribute trace-traffic? to 123e5=0A= PASS: set attribute trace-traffic? to string=0A= PASS: set attribute buffer-while-disconnected? to -1=0A= PASS: set attribute buffer-while-disconnected? to 127.0.0.0:xxx=0A= PASS: set attribute buffer-while-disconnected? to 123e5=0A= PASS: set attribute buffer-while-disconnected? to string=0A= PASS: set attribute connected? to -1=0A= PASS: set attribute connected? to 127.0.0.0:xxx=0A= PASS: set attribute connected? to 123e5=0A= PASS: set attribute connected? to string=0A= PASS: set attribute sockaddr-local to -1=0A= PASS: set attribute sockaddr-local to 127.0.0.0:xxx=0A= PASS: set attribute sockaddr-local to 123e5=0A= PASS: set attribute sockaddr-local to string=0A= PASS: set attribute sockaddr-local to on=0A= PASS: set attribute sockaddr-local to a.b.c.d:e=0A= PASS: set attribute sockaddr-peer to -1=0A= PASS: set attribute sockaddr-peer to 127.0.0.0:xxx=0A= PASS: set attribute sockaddr-peer to 123e5=0A= PASS: set attribute sockaddr-peer to string=0A= PASS: set attribute sockaddr-peer to on=0A= PASS: set attribute sockaddr-peer to a.b.c.d:e=0A= PASS: set attribute init to 127.0.0.0:111=0A= PASS: set attribute init to 123e5=0A= PASS: set attribute init to string=0A= PASS: set attribute init to on=0A= PASS: set attribute fini to 127.0.0.0:111=0A= PASS: set attribute fini to 123e5=0A= PASS: set attribute fini to string=0A= PASS: set attribute fini to on=0A= PASS: set attribute tx to 127.0.0.0:111=0A= PASS: set attribute tx to 123e5=0A= PASS: set attribute tx to string=0A= PASS: set attribute tx to on=0A= PASS: set attribute rx to 127.0.0.0:111=0A= PASS: set attribute rx to 123e5=0A= PASS: set attribute rx to string=0A= PASS: set attribute rx to on=0A= PASS: set attribute tx-count to 123=0A= PASS: set attribute tx-count to 1.1=0A= PASS: set attribute tx-count to 127.0.0.1:123=0A= PASS: set attribute tx-count to yes=0A= PASS: set attribute tx-buffer to 123=0A= PASS: set attribute tx-buffer to 1.1=0A= PASS: set attribute tx-buffer to 127.0.0.1:123=0A= PASS: set attribute tx-buffer to yes=0A= PASS: set attribute rx-count to 123=0A= PASS: set attribute rx-count to 1.1=0A= PASS: set attribute rx-count to 127.0.0.1:123=0A= PASS: set attribute rx-count to yes=0A= PASS: set attribute poll-count to 123=0A= PASS: set attribute poll-count to 1.1=0A= PASS: set attribute poll-count to 127.0.0.1:123=0A= PASS: set attribute poll-count to yes=0A= PASS: set attribute avg-tx-buffer-size to 123=0A= PASS: set attribute avg-tx-buffer-size to 1.1=0A= PASS: set attribute avg-tx-buffer-size to 127.0.0.1:123=0A= PASS: set attribute avg-tx-buffer-size to yes=0A= PASS: set attribute sockaddr-peer to 123=0A= PASS: set attribute sockaddr-peer to 1.1=0A= PASS: set attribute sockaddr-peer to 127.0.0.1:123=0A= PASS: set attribute sockaddr-peer to yes=0A= PASS: set attribute connected? to 123=0A= PASS: set attribute connected? to 1.1=0A= PASS: set attribute connected? to 127.0.0.1:123=0A= PASS: set attribute connected? to yes=0A= PASS: try driving fini pin before driving init pin=0A= PASS: try driving fini pin before driving init pin=0A= PASS: try driving tx pin with -1 when there is no connection=0A= PASS: try driving tx pin with 0 when there is no connection=0A= PASS: try driving tx pin with 255 when there is no connection=0A= PASS: try driving tx pin with 256 when there is no connection=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.consoles/socketval.= exp ...=0A= Running ../../../../src/sid/component/testsuite/sidcomp.consoles/stdio.exp = ...=0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: attribute list=0A= PASS: get stdin pin=0A= PASS: get stdout pin=0A= PASS: get poll pin=0A= PASS: Save state=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.consoles/stdioinv.e= xp ...=0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: find pin that does not exist=0A= PASS: connect to a pin that does not exist=0A= PASS: check connected pins on a pin that does not exist=0A= PASS: check disconnecting pin on a pin that does not exist=0A= PASS: find bus that does not exist=0A= PASS: connect to an accessor that does not exist=0A= PASS: check connected bus on a bus that does not exist=0A= PASS: set relationships that does not exist=0A= PASS: set relationships to relate to a non existing component=0A= PASS: query relationships that does not exist=0A= PASS: set non existing attribute to -1=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.consoles/stdioval.e= xp ...=0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: check attribute list=0A= PASS: check attribute pin list=0A= PASS: check attribute register list=0A= PASS: check attribute setting list=0A= PASS: check attribute watchable list=0A= PASS: check pin names=0A= PASS: check bus names=0A= PASS: check accessor names=0A= PASS: check relationship names=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.gloss/angel.exp ...= =0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: attribute list=0A= PASS: basic attributes present=0A= PASS: set command line=0A= PASS: validate command line=0A= PASS: set heap base=0A= PASS: validate heap base=0A= PASS: set heap limit=0A= PASS: validate heap limit=0A= PASS: set stack base=0A= PASS: validate stack base=0A= PASS: set stack limit=0A= PASS: validate stack limit=0A= PASS: set verbose on=0A= PASS: validate verbose on=0A= PASS: set verbose off=0A= PASS: validate verbose off=0A= PASS: get trap pin=0A= PASS: get trap-code pin=0A= PASS: get fault pin=0A= PASS: get fault-code pin=0A= PASS: get process-signal pin=0A= PASS: test presence of CPU component=0A= PASS: set CPU endianness=0A= PASS: set CPU endianness more=0A= PASS: get memory bus=0A= PASS: open syscall (stdin)=0A= PASS: open syscall (stdout)=0A= PASS: open syscall (mode r)=0A= PASS: open syscall (mode r, missing file)=0A= PASS: open syscall (mode rb)=0A= PASS: open syscall (mode rb, missing file)=0A= PASS: open syscall (mode r+)=0A= PASS: open syscall (mode r+, missing file)=0A= PASS: open syscall (mode r+b)=0A= PASS: open syscall (mode r+b, missing file)=0A= PASS: open syscall (mode w)=0A= PASS: open syscall (mode w, missing file)=0A= PASS: open syscall (mode wb)=0A= PASS: open syscall (mode wb, missing file)=0A= PASS: open syscall (mode w+)=0A= PASS: open syscall (mode w+, missing file)=0A= PASS: open syscall (mode w+b)=0A= PASS: open syscall (mode w+b, missing file)=0A= PASS: open syscall (mode a)=0A= PASS: open syscall (mode a)=0A= PASS: open syscall (mode ab)=0A= PASS: open syscall (mode ab)=0A= PASS: open syscall (mode a+)=0A= PASS: open syscall (mode a+)=0A= PASS: open syscall (mode a+b)=0A= PASS: open syscall (mode a+b)=0A= PASS: open syscall (invalid mode)=0A= PASS: open syscall (for dummy file)=0A= PASS: open syscall (for dummy file)=0A= PASS: close syscall (file on the host)=0A= PASS: close syscall (bad file descriptor)=0A= PASS: writec syscall=0A= PASS: write0 syscall=0A= PASS: write syscall=0A= PASS: readc syscall=0A= PASS: read syscall=0A= PASS: iserror syscall (negative status word)=0A= PASS: iserror syscall (zero status word)=0A= PASS: iserror syscall (positive status word)=0A= PASS: istty syscall (for interactive files)=0A= PASS: istty syscall (for interactive files)=0A= PASS: istty syscall (for non-interactive files)=0A= PASS: istty syscall (bad file descriptor)=0A= PASS: seek syscall=0A= PASS: seek syscall (bad file descriptor)=0A= PASS: flen syscall=0A= PASS: flen syscall (bad file descriptor)=0A= PASS: tmpnam syscall=0A= PASS: remove syscall=0A= PASS: remove syscall (non-existent file)=0A= PASS: rename syscall=0A= PASS: rename syscall (non-existent file)=0A= PASS: clock syscall=0A= PASS: time syscall=0A= PASS: system syscall=0A= PASS: errno syscall=0A= PASS: get-cmdline syscall=0A= PASS: heapinfo syscall=0A= PASS: report exception (exit)=0A= PASS: report exception (abort)=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/attribbank.exp= ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: check initial attribute list=0A= PASS: set testing attributes=0A= PASS: check testing attribute list=0A= PASS: retrieve testing attributes=0A= PASS: overwrite a few testing attributes=0A= PASS: check testing attribute list after overwrite=0A= PASS: retrieve testing attributes after overwrite=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/attribinval.ex= p ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: find pin that does not exist=0A= PASS: connect to a pin that does not exist=0A= PASS: check connected pins on a pin that does not exist=0A= PASS: check disconnecting pin on a pin that does not exist=0A= PASS: find bus that does not exist=0A= PASS: connect to an accessor that does not exist=0A= PASS: check connected bus on a bus that does not exist=0A= PASS: set relationships that does not exist=0A= PASS: query relationships that does not exist=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/attribval.exp = ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: check setting attribute list=0A= PASS: check pin attribute list=0A= PASS: check register attribute list=0A= PASS: check register watchable list=0A= PASS: query pin names=0A= PASS: query bus names=0A= PASS: query accessor names=0A= PASS: query relationships names=0A= PASS: set weird attribute names=0A= PASS: check testing attribute list=0A= PASS: retrieve testing attributes=0A= PASS: set 1000 attributes=0A= PASS: check attributes after setting=0A= PASS: adding another 1000 attributes=0A= PASS: check attributes after setting=0A= PASS: check values for unknown attributes=0A= PASS: check some attribute list after trying to get unknown attribute value= s=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/gluedocs.exp .= ..=0A= PASS: Documentation file (txt) for hw-glue-sequence exists=0A= PASS: Documentation file (xml) for hw-glue-sequence exists=0A= PASS: Documentation file seems to document hw-glue-sequence=0A= PASS: Documentation file (txt) for hw-glue-probe-bus exists=0A= PASS: Documentation file (xml) for hw-glue-probe-bus exists=0A= PASS: Documentation file seems to document hw-glue-probe-bus=0A= PASS: Documentation file (txt) for hw-glue-bus-mux exists=0A= PASS: Documentation file (xml) for hw-glue-bus-mux exists=0A= PASS: Documentation file seems to document hw-glue-bus-mux=0A= PASS: Documentation file (txt) for sw-glue-attribbank exists=0A= PASS: Documentation file (xml) for sw-glue-attribbank exists=0A= PASS: Documentation file seems to document sw-glue-attribbank=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/gluemonkey.exp= ...=0A= PASS: monkey test hw-glue-sequence (30s iterations)=0A= PASS: monkey test sw-glue-attribbank (30s iterations)=0A= PASS: monkey test hw-glue-bus-mux (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/seqinval.exp .= ..=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: attribute list with incorrect category names=0A= PASS: query incorrect attributes name=0A= PASS: set num-outputs to 1*2=0A= PASS: set num-outputs to -1=0A= PASS: set num-outputs to aa=0A= PASS: set num-outputs 1.0123=0A= PASS: set num-outputs true=0A= PASS: set attributes values to non existing attribute=0A= PASS: find pin that does not exist=0A= PASS: connect pin that does not exist=0A= PASS: disconnect pin that does not exist=0A= PASS: check connected pins that does not exist=0A= PASS: connect accessor that does not exist=0A= PASS: find bus that does not exist=0A= PASS: find connected bus that does not exist=0A= PASS: connect accessor to a bus that does not exist=0A= PASS: set relationships that does not exist=0A= PASS: set relationships to relate to a non existing component=0A= PASS: query relationships that does not exist=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/sequence.exp .= ..=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: check attribute list=0A= PASS: get input pin=0A= PASS: set outputs=3D0=0A= PASS: attempt setting bad output=0A= PASS: set outputs=3D10=0A= PASS: set 10 output pins=0A= PASS: drive with value=0A= PASS: shrink output list=0A= PASS: drive after shrinking=0A= PASS: get state snapshot=0A= PASS: restore state snapshot=0A= PASS: prepare for infinite recursion detection test=0A= PASS: infinite recursion detection=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/sequence1.exp = ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: check default num-outputs is 1=0A= PASS: check pin names=0A= PASS: loop through output pins=0A= PASS: num-outputs cannot be changed=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/sequence2.exp = ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: check default num-outputs is 2=0A= PASS: check pin names=0A= PASS: loop through output pins=0A= PASS: num-outputs cannot be changed=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/sequence8.exp = ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: check default num-outputs is 8=0A= PASS: check pin names=0A= PASS: loop through output pins=0A= PASS: num-outputs cannot be changed=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/seqvalid.exp .= ..=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: check attribute list=0A= PASS: check bus names=0A= PASS: check setting attribute list=0A= PASS: check pin attribute list=0A= PASS: check register attribute list=0A= PASS: check register watchable list=0A= PASS: check accessor names=0A= PASS: check relationships names=0A= PASS: check pin names=0A= PASS: get input pin=0A= PASS: erroneously connect input pin=0A= PASS: erroneously check connected input pin=0A= PASS: erroneously disconnect input pin=0A= PASS: check default num-outputs=0A= PASS: set outputs=3D0=0A= PASS: check num-outputs=3D0=0A= PASS: attempt setting bad output=0A= PASS: set outputs=3D10=0A= PASS: check num-outputs=3D10=0A= PASS: check pin names for num-outputs=3D10=0A= PASS: set 10 output pins=0A= PASS: drive with value=0A= PASS: check connected pins=0A= PASS: shrink output list=0A= PASS: drive after shrinking=0A= PASS: disconnect pins=0A= PASS: check connected pins after disconnect pins=0A= PASS: check num-outputs attribute is 200=0A= PASS: set num-outputs too high=0A= PASS: set num-outputs before state snapshot - A=0A= PASS: set num-outputs before state snapshot - B=0A= PASS: get state snapshot=0A= PASS: set num-outputs to 5 after save state=0A= PASS: check num-outputs=3D5 after save state=0A= PASS: restore state snapshot=0A= PASS: check num-outputs=3D17 after restore state=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.glue/traffic.exp ..= .=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: intense attribute traffic=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.ide/diskio.exp ...= =0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: get buses=0A= PASS: configure drive 0=0A= FAIL: read identification for drive 0 - wait 06 0x08 0x08 - unmapped 0=0A= FAIL: read identification for drive 0=0A= FAIL: read identification for nonexistent drive 1 - wait 06 0x01 0x01 - unm= apped 0=0A= FAIL: read identification for nonexistent drive 1=0A= FAIL: write first sector of drive 0 - wait 06 0x08 0x08 - unmapped 0=0A= FAIL: write first sector of drive 0 - wait 06 0x01 0x00 - unmapped 0=0A= FAIL: write first sector of drive 0=0A= FAIL: write second sector of drive 0 using shorts - wait 06 0x08 0x08 - unm= apped 0=0A= FAIL: write second sector of drive 0 using shorts - wait 06 0x01 0x00 - unm= apped 0=0A= FAIL: write second sector of drive 0 using shorts=0A= PASS: configure drive 1=0A= FAIL: copy CHS sectors 0,1 on drive 0 TO LBA sectors 1,0 on drive 1 - wait = 06 0x08 0x08 - unmapped 0=0A= FAIL: copy CHS sectors 0,1 on drive 0 TO LBA sectors 1,0 on drive 1 - wait = 06 0x01 0x00 - unmapped 0=0A= FAIL: copy CHS sectors 0,1 on drive 0 TO LBA sectors 1,0 on drive 1 - wait = 06 0x08 0x08 - unmapped 0=0A= FAIL: copy CHS sectors 0,1 on drive 0 TO LBA sectors 1,0 on drive 1 - wait = 06 0x01 0x00 - unmapped 0=0A= FAIL: copy CHS sectors 0,1 on drive 0 TO LBA sectors 1,0 on drive 1 - wait = 06 0x08 0x08 - unmapped 0=0A= FAIL: copy CHS sectors 0,1 on drive 0 TO LBA sectors 1,0 on drive 1 - wait = 06 0x01 0x00 - unmapped 0=0A= FAIL: copy CHS sectors 0,1 on drive 0 TO LBA sectors 1,0 on drive 1 - wait = 06 0x08 0x08 - unmapped 0=0A= FAIL: copy CHS sectors 0,1 on drive 0 TO LBA sectors 1,0 on drive 1 - wait = 06 0x01 0x00 - unmapped 0=0A= FAIL: copy CHS sectors 0,1 on drive 0 TO LBA sectors 1,0 on drive 1=0A= PASS: shut down ide drive models=0A= PASS: check contents of diskio.drive1=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.ide/idebase.exp ...= =0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: save state snapshot=0A= PASS: restore state snapshot=0A= PASS: compare new state snapshot=0A= PASS: set toughie state parameters=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.ide/idedocs.exp ...= =0A= PASS: Documentation file (txt) for hw-disk-ide exists=0A= PASS: Documentation file (xml) for hw-disk-ide exists=0A= PASS: Documentation file seems to document hw-disk-ide=0A= Running ../../../../src/sid/component/testsuite/sidcomp.ide/idetrigger.exp = ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: fetch attribute categories=0A= PASS: prepare watch signalling pins=0A= PASS: obsolete watch pin syntax=0A= PASS: watch an ordinary passive r/w attribute for changes=0A= PASS: stop watching it=0A= PASS: watch an ordinary passive r/w register for mask/value match=0A= PASS: stop watching that too=0A= PASS: watch same register with several separate triggerpoints=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.interrupt/arm-inter= rupt.exp ...=0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: establish a triggerpoint for watchable state variable: interrupt=0A= PASS: establish a triggerpoint for watchable state variable: fast-interrupt= =0A= PASS: establish a triggerpoint for watchable state variable: irq-raw-status= =0A= PASS: establish a triggerpoint for watchable state variable: irq-enable-reg= ister=0A= PASS: establish a triggerpoint for watchable state variable: fiq-raw-status= =0A= PASS: establish a triggerpoint for watchable state variable: fiq-enable-reg= ister=0A= PASS: attribute list=0A= PASS: get fast-irq pin=0A= PASS: get irq pin=0A= PASS: get reset pin=0A= PASS: get fast interrupt source pin=0A= PASS: get interrupt-source-0 pin=0A= PASS: get interrupt-source-1 pin=0A= PASS: get interrupt-source-2 pin=0A= PASS: get interrupt-source-3 pin=0A= PASS: get interrupt-source-4 pin=0A= PASS: get interrupt-source-5 pin=0A= PASS: get interrupt-source-6 pin=0A= PASS: get interrupt-source-7 pin=0A= PASS: get interrupt-source-8 pin=0A= PASS: get interrupt-source-9 pin=0A= PASS: get interrupt-source-10 pin=0A= PASS: get interrupt-source-11 pin=0A= PASS: get interrupt-source-12 pin=0A= PASS: get interrupt-source-13 pin=0A= PASS: get interrupt-source-14 pin=0A= PASS: get interrupt-source-15 pin=0A= PASS: get interrupt-source-16 pin=0A= PASS: get interrupt-source-17 pin=0A= PASS: get interrupt-source-18 pin=0A= PASS: get interrupt-source-19 pin=0A= PASS: get interrupt-source-20 pin=0A= PASS: get interrupt-source-21 pin=0A= PASS: get interrupt-source-22 pin=0A= PASS: get interrupt-source-23 pin=0A= PASS: get interrupt-source-24 pin=0A= PASS: get interrupt-source-25 pin=0A= PASS: get interrupt-source-26 pin=0A= PASS: get interrupt-source-27 pin=0A= PASS: get interrupt-source-28 pin=0A= PASS: get interrupt-source-29 pin=0A= PASS: get interrupt-source-30 pin=0A= PASS: get interrupt-source-31 pin=0A= PASS: get irq-register bus=0A= PASS: get fiq-register bus=0A= PASS: writing to reserved irq-register (offset 0x0)=0A= PASS: writing to reserved irq-register (offset 0x1)=0A= PASS: writing to reserved fiq-register (offset 0x0)=0A= PASS: writing to reserved fiq-register (offset 0x4)=0A= PASS: reading from reserved irq-register (offset 0xC)=0A= PASS: reading from reserved irq-register (offset 0x10)=0A= PASS: reading from reserved fiq-register (offset 0x10C)=0A= PASS: Save state=0A= PASS: disable all interrupt lines=0A= PASS: validate all interrupt lines are disabled=0A= PASS: initialise set of enabled interrupt lines=0A= PASS: validate set of enabled interrupt lines=0A= PASS: disable all interrupt lines=0A= PASS: validate all interrupt lines are disabled=0A= PASS: initialise set of enabled interrupt lines=0A= PASS: validate set of enabled interrupt lines=0A= PASS: disable all interrupt lines=0A= PASS: validate all interrupt lines are disabled=0A= PASS: initialise set of enabled interrupt lines=0A= PASS: validate set of enabled interrupt lines=0A= PASS: disable all interrupt lines=0A= PASS: validate all interrupt lines are disabled=0A= PASS: initialise set of enabled interrupt lines=0A= PASS: validate set of enabled interrupt lines=0A= PASS: disable all interrupt lines=0A= PASS: validate all interrupt lines are disabled=0A= PASS: initialise set of enabled interrupt lines=0A= PASS: validate set of enabled interrupt lines=0A= PASS: Repeat Save state=0A= PASS: Restore State=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 0=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 1=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 2=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 3=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 4=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 5=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 6=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 7=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 8=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 9=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 10=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 11=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 12=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 13=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 14=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 15=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 16=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 17=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 18=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 19=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 20=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 21=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 22=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 23=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 24=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 25=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 26=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 27=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 28=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 29=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 30=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 31=0A= PASS: interrupt masking=0A= PASS: disable fast interrupt=0A= PASS: validate fast interrupt disabled=0A= PASS: enable fast interrupt=0A= PASS: validate fast interrupt is enabled=0A= PASS: fast interrupt=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 1 only=0A= PASS: programmed interrupt=0A= PASS: interrupt triggerpoint fired 69 times=0A= PASS: fast-interrupt triggerpoint fired 3 times=0A= PASS: irq-raw-status triggerpoint fired 2049 times=0A= PASS: irq-enable-register triggerpoint fired 73 times=0A= PASS: fiq-raw-status triggerpoint fired twice=0A= PASS: fiq-enable-register triggerpoint fired once=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.interrupt/cma222-in= terrupt.exp ...=0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: establish a triggerpoint for watchable state variable: interrupt=0A= PASS: establish a triggerpoint for watchable state variable: irq-raw-status= =0A= PASS: establish a triggerpoint for watchable state variable: irq-enable-reg= ister=0A= PASS: attribute list=0A= PASS: get irq pin=0A= PASS: get interrupt-source-0 pin=0A= PASS: get interrupt-source-1 pin=0A= PASS: get interrupt-source-2 pin=0A= PASS: get interrupt-source-3 pin=0A= PASS: get interrupt-source-4 pin=0A= PASS: get interrupt-source-5 pin=0A= PASS: get interrupt-source-6 pin=0A= PASS: get interrupt-source-7 pin=0A= PASS: get irq-register bus=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 0=0A= PASS: validate interrupt 0 is still enabled=0A= PASS: validate interrupt 0 is still enabled=0A= PASS: masking interrupt from interrupt 3 when enabling interrupt 0 only=0A= PASS: masking interrupt from interrupt 4 when enabling interrupt 0 only=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 1=0A= PASS: masking interrupt from interrupt 0 when enabling interrupt 1 only=0A= PASS: masking interrupt from interrupt 3 when enabling interrupt 1 only=0A= PASS: masking interrupt from interrupt 4 when enabling interrupt 1 only=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 2=0A= PASS: masking interrupt from interrupt 0 when enabling interrupt 2 only=0A= PASS: masking interrupt from interrupt 3 when enabling interrupt 2 only=0A= PASS: masking interrupt from interrupt 4 when enabling interrupt 2 only=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 3=0A= PASS: masking interrupt from interrupt 0 when enabling interrupt 3 only=0A= PASS: validate interrupt 3 is still enabled=0A= PASS: validate interrupt 3 is still enabled=0A= PASS: masking interrupt from interrupt 4 when enabling interrupt 3 only=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 4=0A= PASS: masking interrupt from interrupt 0 when enabling interrupt 4 only=0A= PASS: masking interrupt from interrupt 3 when enabling interrupt 4 only=0A= PASS: validate interrupt 4 is still enabled=0A= PASS: validate interrupt 4 is still enabled=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 5=0A= PASS: masking interrupt from interrupt 0 when enabling interrupt 5 only=0A= PASS: masking interrupt from interrupt 3 when enabling interrupt 5 only=0A= PASS: masking interrupt from interrupt 4 when enabling interrupt 5 only=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 6=0A= PASS: masking interrupt from interrupt 0 when enabling interrupt 6 only=0A= PASS: masking interrupt from interrupt 3 when enabling interrupt 6 only=0A= PASS: masking interrupt from interrupt 4 when enabling interrupt 6 only=0A= PASS: disable all interrupt lines=0A= PASS: enable interrupt line 7=0A= PASS: masking interrupt from interrupt 0 when enabling interrupt 7 only=0A= PASS: masking interrupt from interrupt 3 when enabling interrupt 7 only=0A= PASS: masking interrupt from interrupt 4 when enabling interrupt 7 only=0A= PASS: interrupt masking=0A= PASS: interrupt triggerpoint fired 17 times=0A= PASS: irq-raw-status triggerpoint fired 128 times=0A= PASS: irq-enable-register triggerpoint fired 15 times=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.interrupt/interrupt= docs.exp ...=0A= PASS: Documentation file (txt) for hw-interrupt-arm/ref exists=0A= PASS: Documentation file (xml) for hw-interrupt-arm/ref exists=0A= PASS: Documentation file seems to document hw-interrupt-arm/ref=0A= PASS: Documentation file (txt) for hw-interrupt-cogent/cma222 exists=0A= PASS: Documentation file (xml) for hw-interrupt-cogent/cma222 exists=0A= PASS: Documentation file seems to document hw-interrupt-cogent/cma222=0A= Running ../../../../src/sid/component/testsuite/sidcomp.interrupt/interrupt= monkey.exp ...=0A= PASS: monkey test hw-interrupt-arm/ref (30s iterations)=0A= PASS: monkey test hw-interrupt-cogent/cma222 (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.lcd/lcd1inv.exp ...= =0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: set width to 10000000000000000=0A= PASS: set width to 10000000000000000=0A= PASS: set width to xyz=0A= PASS: set width to xyz=0A= PASS: set width to FALSE=0A= PASS: set width to FALSE=0A= PASS: set width to 1.234e-10=0A= PASS: set width to 1.234e-10=0A= PASS: set width to -1=0A= PASS: set height to -1=0A= PASS: set width to 0=0A= PASS: set height to 0=0A= PASS: query incorrect attributes name=0A= PASS: set attributes values to non existing attribute=0A= PASS: find pin that does not exist=0A= PASS: connect pin that does not exist=0A= PASS: disconnect pin that does not exist=0A= PASS: check connected pins that does not exist=0A= PASS: connect accessor that does not exist=0A= PASS: find bus that does not exist=0A= PASS: find connected bus that does not exist=0A= PASS: set relationships that does not exist=0A= PASS: query relationships that does not exist=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.lcd/lcd1val.exp ...= =0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: initialise=0A= PASS: check attribute list=0A= PASS: check pin attribute list=0A= PASS: check register attribute list=0A= PASS: check watchable attribute list=0A= PASS: check setting attribute list=0A= PASS: check default value for width=0A= PASS: check default value for height=0A= PASS: get FR pin=0A= PASS: drive FR pin with 0=0A= PASS: drive FR pin with 1=0A= PASS: get row-col pin=0A= PASS: drive row-col pin with 0=0A= PASS: drive row-col pin with 1=0A= PASS: drive row-col pin with 2=0A= PASS: drive row-col pin with 3=0A= PASS: drive row-col pin with 4=0A= PASS: drive row-col pin with 5=0A= PASS: drive row-col pin with 6=0A= PASS: drive row-col pin with 7=0A= PASS: drive row-col pin with 8=0A= PASS: drive row-col pin with 9=0A= PASS: Save state=0A= PASS: Change the width setting to 100=0A= PASS: Check the width setting=0A= PASS: Change the height setting to 12=0A= PASS: Check the height setting=0A= PASS: Restore previous state=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.lcd/lcdbase.exp ...= =0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: acquire bus=0A= PASS: Save state=0A= PASS: get display row-col pin=0A= PASS: correct AC value after DR write=0A= PASS: correct AC value after 2nd DR write=0A= PASS: DR read=0A= PASS: AC read=0A= PASS: draw Cygnus logo=0A= PASS: Restore state=0A= PASS: get display row-col pin=0A= PASS: correct AC value after DR write=0A= PASS: correct AC value after 2nd DR write=0A= PASS: DR read=0A= PASS: AC read=0A= PASS: draw Cygnus logo=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.lcd/lcdmonkey.exp .= ..=0A= PASS: monkey test hw-lcd-hd44780u-a00 (30s iterations)=0A= PASS: monkey test hw-lcd-hd44780u-a02 (30s iterations)=0A= WARNING: monkey test hw-lcd-t6963c-0201 - state restore failed=0A= WARNING: monkey test hw-lcd-t6963c-0201 - state restore did not preserve ro= w-col=0A= WARNING: monkey test hw-lcd-t6963c-0201 - state restore did not preserve GA= =0A= WARNING: monkey test hw-lcd-t6963c-0201 - state restore did not preserve re= fresh-period-msec=0A= WARNING: monkey test hw-lcd-t6963c-0201 - state restore did not preserve FR= =0A= UNRESOLVED: monkey test hw-lcd-t6963c-0201 (30s iterations)=0A= WARNING: monkey test hw-lcd-t6963c-0101 - state restore failed=0A= WARNING: monkey test hw-lcd-t6963c-0101 - state restore did not preserve GA= =0A= WARNING: monkey test hw-lcd-t6963c-0101 - state restore did not preserve ro= w-col=0A= WARNING: monkey test hw-lcd-t6963c-0101 - state restore did not preserve FR= =0A= WARNING: monkey test hw-lcd-t6963c-0101 - state restore did not preserve re= fresh-period-msec=0A= UNRESOLVED: monkey test hw-lcd-t6963c-0101 (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.loader/loader.exp .= ..=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: attribute list=0A= PASS: set file =3D x32.x=0A= PASS: load x32.x=0A= PASS: set file =3D x64.x=0A= PASS: load x64.x=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.mapper/basicmapper.= exp ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: all attributes are present=0A= PASS: access-port bus is present=0A= PASS: acquire mapper bus handle=0A= PASS: no known accessors at startup=0A= PASS: generate test bus #1=0A= PASS: generate test bus #2=0A= PASS: generate test bus #3=0A= PASS: generate test bus #4=0A= PASS: connect test bus #1 to the mapper=0A= PASS: prior accessor is now registered=0A= PASS: connect an accessor with an invalid name: abc=0A= PASS: connect an accessor with an invalid name: [foo]=0A= PASS: connect an accessor with an invalid name: [bar=0A= PASS: connect an accessor with an invalid name: [0,abc]=0A= PASS: connect an accessor with an invalid name: [zog]=0A= PASS: connect an accessor with an invalid name: [0-foo]=0A= PASS: connect an accessor with an invalid name: [0--foo]=0A= PASS: connect an accessor with an invalid name: [0x100-0x200,3,1]=0A= PASS: connect an accessor with an invalid name: [0x100-0x200,1,3]=0A= PASS: connect an accessor with an invalid name: [0x100]{a}=0A= PASS: connect an accessor with an invalid name: [1-2]{}=0A= PASS: only one accessor is still registered=0A= PASS: connect test bus #2 to the mapper=0A= PASS: connect test bus #3 to the mapper=0A= PASS: connect test bus #4 to the mapper=0A= PASS: four accessors are now registered=0A= PASS: detect & reject overlapping address ranges=0A= PASS: disconnect existing accessors--to start afresh=0A= PASS: establish many 1-byte wide accessors for testing=0A= PASS: establish many 2-byte wide accessors for testing=0A= PASS: establish many 4-byte wide accessors for testing=0A= PASS: establish many 8-byte wide accessors for testing=0A= PASS: simple walk along bus (aligned 1-byte reads/writes) with stride 1=0A= PASS: simple walk along bus (aligned 1-byte reads/writes) with stride 2=0A= PASS: simple walk along bus (aligned 1-byte reads/writes) with stride 4=0A= PASS: simple walk along bus (aligned 1-byte reads/writes) with stride 8=0A= PASS: simple walk along bus (aligned 1-byte reads/writes) with stride 16=0A= PASS: simple walk along bus (aligned 1-byte reads/writes) with stride 32=0A= PASS: simple walk along bus (aligned 1-byte reads/writes) with stride 64=0A= PASS: simple walk along bus (aligned 1-byte reads/writes) with stride 128= =0A= PASS: simple walk along bus (aligned 1-byte reads/writes) with stride 256= =0A= PASS: simple walk along bus (aligned 2-byte reads/writes) with stride 2=0A= PASS: simple walk along bus (aligned 2-byte reads/writes) with stride 4=0A= PASS: simple walk along bus (aligned 2-byte reads/writes) with stride 8=0A= PASS: simple walk along bus (aligned 2-byte reads/writes) with stride 16=0A= PASS: simple walk along bus (aligned 2-byte reads/writes) with stride 32=0A= PASS: simple walk along bus (aligned 2-byte reads/writes) with stride 64=0A= PASS: simple walk along bus (aligned 2-byte reads/writes) with stride 128= =0A= PASS: simple walk along bus (aligned 2-byte reads/writes) with stride 256= =0A= PASS: simple walk along bus (aligned 4-byte reads/writes) with stride 4=0A= PASS: simple walk along bus (aligned 4-byte reads/writes) with stride 8=0A= PASS: simple walk along bus (aligned 4-byte reads/writes) with stride 16=0A= PASS: simple walk along bus (aligned 4-byte reads/writes) with stride 32=0A= PASS: simple walk along bus (aligned 4-byte reads/writes) with stride 64=0A= PASS: simple walk along bus (aligned 4-byte reads/writes) with stride 128= =0A= PASS: simple walk along bus (aligned 4-byte reads/writes) with stride 256= =0A= PASS: simple walk along bus (aligned 8-byte reads/writes) with stride 8=0A= PASS: simple walk along bus (aligned 8-byte reads/writes) with stride 16=0A= PASS: simple walk along bus (aligned 8-byte reads/writes) with stride 32=0A= PASS: simple walk along bus (aligned 8-byte reads/writes) with stride 64=0A= PASS: simple walk along bus (aligned 8-byte reads/writes) with stride 128= =0A= PASS: simple walk along bus (aligned 8-byte reads/writes) with stride 256= =0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 1 wid= th 1=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 1 wid= th 1=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 1 wid= th 1=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 1 wid= th 1=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 2 wid= th 1=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 2 wid= th 1=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 2 wid= th 1=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 2 wid= th 1=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 4 wid= th 1=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 4 wid= th 1=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 4 wid= th 1=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 4 wid= th 1=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 8 wid= th 1=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 8 wid= th 1=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 8 wid= th 1=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 8 wid= th 1=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 16 wi= dth 1=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 16 wi= dth 1=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 16 wi= dth 1=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 16 wi= dth 1=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 32 wi= dth 1=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 32 wi= dth 1=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 32 wi= dth 1=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 32 wi= dth 1=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 64 wi= dth 1=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 64 wi= dth 1=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 64 wi= dth 1=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 64 wi= dth 1=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 128 w= idth 1=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 128 w= idth 1=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 128 w= idth 1=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 128 w= idth 1=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 256 w= idth 1=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 256 w= idth 1=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 256 w= idth 1=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 256 w= idth 1=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 2 wid= th 2=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 2 wid= th 2=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 2 wid= th 2=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 2 wid= th 2=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 4 wid= th 2=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 4 wid= th 2=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 4 wid= th 2=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 4 wid= th 2=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 8 wid= th 2=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 8 wid= th 2=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 8 wid= th 2=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 8 wid= th 2=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 16 wi= dth 2=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 16 wi= dth 2=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 16 wi= dth 2=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 16 wi= dth 2=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 32 wi= dth 2=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 32 wi= dth 2=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 32 wi= dth 2=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 32 wi= dth 2=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 64 wi= dth 2=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 64 wi= dth 2=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 64 wi= dth 2=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 64 wi= dth 2=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 128 w= idth 2=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 128 w= idth 2=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 128 w= idth 2=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 128 w= idth 2=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 256 w= idth 2=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 256 w= idth 2=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 256 w= idth 2=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 256 w= idth 2=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 4 wid= th 4=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 4 wid= th 4=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 4 wid= th 4=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 4 wid= th 4=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 8 wid= th 4=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 8 wid= th 4=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 8 wid= th 4=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 8 wid= th 4=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 16 wi= dth 4=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 16 wi= dth 4=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 16 wi= dth 4=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 16 wi= dth 4=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 32 wi= dth 4=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 32 wi= dth 4=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 32 wi= dth 4=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 32 wi= dth 4=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 64 wi= dth 4=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 64 wi= dth 4=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 64 wi= dth 4=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 64 wi= dth 4=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 128 w= idth 4=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 128 w= idth 4=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 128 w= idth 4=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 128 w= idth 4=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 256 w= idth 4=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 256 w= idth 4=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 256 w= idth 4=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 256 w= idth 4=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 8 wid= th 8=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 8 wid= th 8=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 8 wid= th 8=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 8 wid= th 8=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 16 wi= dth 8=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 16 wi= dth 8=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 16 wi= dth 8=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 16 wi= dth 8=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 32 wi= dth 8=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 32 wi= dth 8=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 32 wi= dth 8=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 32 wi= dth 8=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 64 wi= dth 8=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 64 wi= dth 8=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 64 wi= dth 8=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 64 wi= dth 8=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 128 w= idth 8=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 128 w= idth 8=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 128 w= idth 8=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 128 w= idth 8=0A= PASS: width-adjusted walk along bus (1-byte reads/writes) with stride 256 w= idth 8=0A= PASS: width-adjusted walk along bus (2-byte reads/writes) with stride 256 w= idth 8=0A= PASS: width-adjusted walk along bus (4-byte reads/writes) with stride 256 w= idth 8=0A= PASS: width-adjusted walk along bus (8-byte reads/writes) with stride 256 w= idth 8=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.mapper/busif.exp ..= .=0A= UNTESTED: busif component not available for static tests=0A= Running ../../../../src/sid/component/testsuite/sidcomp.mapper/mapperdocs.e= xp ...=0A= PASS: Documentation file (txt) for hw-mapper-basic exists=0A= PASS: Documentation file (xml) for hw-mapper-basic exists=0A= PASS: Documentation file seems to document hw-mapper-basic=0A= Running ../../../../src/sid/component/testsuite/sidcomp.mapper/mappermonkey= .exp ...=0A= PASS: monkey test hw-mapper-basic (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.memory/am29.exp ...= =0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: attribute list=0A= PASS: read-write-port bus is present=0A= PASS: set an invalid sector size of 0 bytes=0A= PASS: set an invalid sector size of 123456789 bytes=0A= PASS: set and validate sector size of 16 bytes=0A= PASS: set and validate sector size of 32 bytes=0A= PASS: set and validate sector size of 128 bytes=0A= PASS: set and validate sector size of 256 bytes=0A= PASS: set and validate sector size of 512 bytes=0A= PASS: set and validate sector size of 1024 bytes=0A= PASS: validate memory is fully erased from the factory=0A= PASS: initial mode is READ (0)=0A= PASS: enter autoselect mode=0A= PASS: return to read mode=0A= PASS: invalid unlock1 sequence sends device to read mode=0A= PASS: invalid unlock2 sequence sends device to read mode=0A= PASS: issue reset command=0A= PASS: read manufacturer code without entering autoselect mode=0A= PASS: read device id code without entering autoselect mode=0A= PASS: read manufacturer code=0A= PASS: read device id code for a typical flash (id=3D0x4F)=0A= PASS: read sector protect verify status for each sector address=0A= PASS: return to read mode=0A= PASS: set size to 512 bytes=0A= PASS: validate size is 512 bytes=0A= PASS: test for memory leaks=0A= PASS: set memory size to 8192 bytes=0A= PASS: set sector size to 256 bytes=0A= PASS: chip erase sets all ones=0A= PASS: write a single byte=0A= PASS: write lots of bytes across sector boundaries=0A= PASS: write lots of bytes across sector boundaries=0A= PASS: write lots of bytes across sector boundaries=0A= PASS: write lots of bytes across sector boundaries=0A= PASS: write lots of bytes across sector boundaries=0A= PASS: write lots of bytes across sector boundaries=0A= PASS: write lots of bytes across sector boundaries=0A= PASS: write lots of bytes across sector boundaries=0A= PASS: write lots of bytes across sector boundaries=0A= PASS: write lots of bytes across sector boundaries=0A= PASS: validate freshly written bytes=0A= PASS: validate freshly written bytes=0A= PASS: validate freshly written bytes=0A= PASS: validate freshly written bytes=0A= PASS: validate freshly written bytes=0A= PASS: validate freshly written bytes=0A= PASS: validate freshly written bytes=0A= PASS: validate freshly written bytes=0A= PASS: validate freshly written bytes=0A= PASS: enter unlock bypass mode=0A= PASS: reset from unlock bypass mode to read mode=0A= PASS: a zero cannot be reset to a one in any location=0A= PASS: sector erase=0A= PASS: read memory image from a file=0A= PASS: verify read memory image=0A= PASS: save state=0A= PASS: restore state=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.memory/at29.exp ...= =0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: attribute list=0A= PASS: read-write-port bus is present=0A= PASS: set size to 512 bytes=0A= PASS: validate size is 512 bytes=0A= PASS: test for memory leaks=0A= PASS: set memory size to 8192 bytes=0A= PASS: set an invalid sector size of 0 bytes=0A= PASS: set an invalid sector size of 8193 bytes=0A= PASS: set and validate sector size of 16 bytes=0A= PASS: set and validate sector size of 32 bytes=0A= PASS: set and validate sector size of 128 bytes=0A= PASS: set and validate sector size of 256 bytes=0A= PASS: set and validate sector size of 512 bytes=0A= PASS: set and validate sector size of 1024 bytes=0A= PASS: set sector size to 256 bytes=0A= PASS: validate sector size is 256 bytes=0A= PASS: read memory image from a file=0A= PASS: verify read memory image=0A= PASS: unpermitted write to address 0x0 has no effect=0A= PASS: unpermitted write to address 0x100 has no effect=0A= PASS: unpermitted write to address 0x1E0 has no effect=0A= PASS: unpermitted write to address 0x20F has no effect=0A= PASS: unpermitted write to address 0x222 has no effect=0A= PASS: unpermitted write to address 0x29A has no effect=0A= PASS: unpermitted write to address 0x4BC has no effect=0A= PASS: unpermitted write to address 0x551 has no effect=0A= PASS: unpermitted write to address 0x555 has no effect=0A= PASS: unpermitted write to address 0x6B0 has no effect=0A= PASS: unpermitted write to address 0x1010 has no effect=0A= PASS: unpermitted write to address 0x10FF has no effect=0A= PASS: writing magic bytes to disable software data protection=0A= PASS: validate the first sector=0A= PASS: illegitimately program the second sector=0A= PASS: validate the second sector -- writes should have no effect=0A= PASS: writing magic bytes to disable software data protection (2)=0A= PASS: validate the third sector=0A= PASS: read manufacturer code without issuing id command=0A= PASS: writing magic bytes to enter identification mode=0A= PASS: read manufacturer code=0A= PASS: read device id code for a low-voltage flash (id=3D0x3B)=0A= PASS: return to normal operating mode=0A= PASS: check for normal operating mode=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.memory/at29inv.exp = ...=0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: try to set size-max=0A= PASS: set size to 10000000000000000=0A= PASS: set size to size-max+1=0A= PASS: set size to -1=0A= PASS: set size to abcdefghijklmn=0A= PASS: set size to FALSE=0A= PASS: set size to 1.234e-10=0A= PASS: set size to 0=0A= PASS: set sector-size to -1=0A= PASS: set sector-size to 0=0A= PASS: set sector-size to 10000000000000000=0A= PASS: set sector-size to xyz=0A= PASS: set sector-size to FALSE=0A= PASS: set sector-size to 1.234e-10=0A= PASS: set device-code to 0x100=0A= PASS: set device-code to -1=0A= PASS: set device-code to 10000000000000000=0A= PASS: set device-code to xyz=0A= PASS: set device-code to FALSE=0A= PASS: set device-code to 1.234e-10=0A= PASS: set sector-size bigger than size=20=0A= PASS: drive image-load with unset image-file attribute=0A= PASS: drive image-store with unset image-file attribute=0A= PASS: attribute list with incorrect category names=0A= PASS: query incorrect attributes name=0A= PASS: set attributes values to non existing attribute=0A= PASS: find pin that does not exist=0A= PASS: connect pin that does not exist=0A= PASS: disconnect pin that does not exist=0A= PASS: check connected pins that does not exist=0A= PASS: connect read-write-port as a accessor=0A= PASS: check connected read-write-port bus=0A= PASS: connect accessor that does not exist=0A= PASS: find bus that does not exist=0A= PASS: find connected bus that does not exist=0A= PASS: set relationships that does not exist=0A= PASS: query relationships that does not exist=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.memory/at29val.exp = ...=0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: check setting attribute list=0A= PASS: check pin attribute list=0A= PASS: check register attribute list=0A= PASS: check watchable attribute list=0A= PASS: check pin names=0A= PASS: check bus names=0A= PASS: check accessor names=0A= PASS: check relationships=0A= PASS: check default device-code is 0x5B=0A= PASS: check default manufacturer-code is 0x1F=0A= PASS: check default size is 524288=0A= PASS: check default sector-size is 512=0A= PASS: try to set manufacturer-code to 0x2F=0A= PASS: check size-max=0A= PASS: set size to size-max=0A= PASS: set size to size-max-1=0A= PASS: set sector-size to 1=0A= PASS: set sector-size to 0=0A= PASS: set device-code to 0x01=0A= PASS: set device-code to 0x00=0A= PASS: read memory image from a file that contains more bytes than the size= =0A= PASS: verify after image-load=0A= PASS: read memory image from a file that contains less bytes than the size= =0A= PASS: verify after image-load II=0A= PASS: set memory before image-store=0A= PASS: drive image-store=0A= PASS: reset memory after image-store=0A= PASS: load the stored image and verify values=0A= PASS: find image-store pin=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.memory/at29xx.exp .= ..=0A= PASS: at29c256 :sid configuration=0A= PASS: at29c256 :sid start=0A= PASS: at29c256 :validate size is 32*1024 bytes=0A= PASS: at29c256 :validate sector-size is 64=0A= PASS: at29c256 :validate device-code is 0xDC=0A= PASS: at29c256 :sid stop=0A= PASS: at29lv256 :sid configuration=0A= PASS: at29lv256 :sid start=0A= PASS: at29lv256 :validate size is 32*1024 bytes=0A= PASS: at29lv256 :validate sector-size is 64=0A= PASS: at29lv256 :validate device-code is 0xBC=0A= PASS: at29lv256 :sid stop=0A= PASS: at29c257 :sid configuration=0A= PASS: at29c257 :sid start=0A= PASS: at29c257 :validate size is 32*1024 bytes=0A= PASS: at29c257 :validate sector-size is 64=0A= PASS: at29c257 :validate device-code is 0xDC=0A= PASS: at29c257 :sid stop=0A= PASS: at29c512 :sid configuration=0A= PASS: at29c512 :sid start=0A= PASS: at29c512 :validate size is 64*1024 bytes=0A= PASS: at29c512 :validate sector-size is 128=0A= PASS: at29c512 :validate device-code is 0x5D=0A= PASS: at29c512 :sid stop=0A= PASS: at29lv512 :sid configuration=0A= PASS: at29lv512 :sid start=0A= PASS: at29lv512 :validate size is 64*1024 bytes=0A= PASS: at29lv512 :validate sector-size is 128=0A= PASS: at29lv512 :validate device-code is 0x3D=0A= PASS: at29lv512 :sid stop=0A= PASS: at29c010a :sid configuration=0A= PASS: at29c010a :sid start=0A= PASS: at29c010a :validate size is 128*1024 bytes=0A= PASS: at29c010a :validate sector-size is 128=0A= PASS: at29c010a :validate device-code is 0xD5=0A= PASS: at29c010a :sid stop=0A= PASS: at29lv010a :sid configuration=0A= PASS: at29lv010a :sid start=0A= PASS: at29lv010a :validate size is 128*1024 bytes=0A= PASS: at29lv010a :validate sector-size is 128=0A= PASS: at29lv010a :validate device-code is 0x35=0A= PASS: at29lv010a :sid stop=0A= PASS: at29bv010a :sid configuration=0A= PASS: at29bv010a :sid start=0A= PASS: at29bv010a :validate size is 128*1024 bytes=0A= PASS: at29bv010a :validate sector-size is 128=0A= PASS: at29bv010a :validate device-code is 0x35=0A= PASS: at29bv010a :sid stop=0A= PASS: at29c020 :sid configuration=0A= PASS: at29c020 :sid start=0A= PASS: at29c020 :validate size is 256*1024 bytes=0A= PASS: at29c020 :validate sector-size is 256=0A= PASS: at29c020 :validate device-code is 0xDA=0A= PASS: at29c020 :sid stop=0A= PASS: at29lv020 :sid configuration=0A= PASS: at29lv020 :sid start=0A= PASS: at29lv020 :validate size is 256*1024 bytes=0A= PASS: at29lv020 :validate sector-size is 256=0A= PASS: at29lv020 :validate device-code is 0xBA=0A= PASS: at29lv020 :sid stop=0A= PASS: at29bv020 :sid configuration=0A= PASS: at29bv020 :sid start=0A= PASS: at29bv020 :validate size is 256*1024 bytes=0A= PASS: at29bv020 :validate sector-size is 256=0A= PASS: at29bv020 :validate device-code is 0xBA=0A= PASS: at29bv020 :sid stop=0A= PASS: at29c040a :sid configuration=0A= PASS: at29c040a :sid start=0A= PASS: at29c040a :validate size is 512*1024 bytes=0A= PASS: at29c040a :validate sector-size is 512=0A= PASS: at29c040a :validate device-code is 0x5B=0A= PASS: at29c040a :sid stop=0A= PASS: at29lv040 :sid configuration=0A= PASS: at29lv040 :sid start=0A= PASS: at29lv040 :validate size is 512*1024 bytes=0A= PASS: at29lv040 :validate sector-size is 512=0A= PASS: at29lv040 :validate device-code is 0x3B=0A= PASS: at29lv040 :sid stop=0A= PASS: at29bv040 :sid configuration=0A= PASS: at29bv040 :sid start=0A= PASS: at29bv040 :validate size is 512*1024 bytes=0A= PASS: at29bv040 :validate sector-size is 512=0A= PASS: at29bv040 :validate device-code is 0x3B=0A= PASS: at29bv040 :sid stop=0A= PASS: at29c040a :sid configuration=0A= PASS: at29c040a :sid start=0A= PASS: at29c040a :validate size is 512*1024 bytes=0A= PASS: at29c040a :validate sector-size is 256=0A= PASS: at29c040a :validate device-code is 0xA4=0A= PASS: at29c040a :sid stop=0A= PASS: at29lv040a :sid configuration=0A= PASS: at29lv040a :sid start=0A= PASS: at29lv040a :validate size is 512*1024 bytes=0A= PASS: at29lv040a :validate sector-size is 256=0A= PASS: at29lv040a :validate device-code is 0xC4=0A= PASS: at29lv040a :sid stop=0A= PASS: at29bv040a :sid configuration=0A= PASS: at29bv040a :sid start=0A= PASS: at29bv040a :validate size is 512*1024 bytes=0A= PASS: at29bv040a :validate sector-size is 256=0A= PASS: at29bv040a :validate device-code is 0xC4=0A= PASS: at29bv040a :sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.memory/genericmemor= y.exp ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: attribute list=0A= PASS: set size =3D 512=0A= PASS: get buses=0A= PASS: fill memory with junk bytes=0A= PASS: read junk from memory via read-only port=0A= PASS: get memory state dump=0A= PASS: reset memory size=0A= PASS: spot check clear memory=0A= FAIL: set memory state dump=0A= PASS: check memory size after restore=0A= FAIL: reread junk from memory after restore - mismatch @ 3 - 192 vs 0=0A= FAIL: reread junk from memory after restore=0A= PASS: test for memory leaks=0A= PASS: resize memory for file test=0A= PASS: read memory image from a file=0A= PASS: verify read memory image=0A= PASS: make a big memory buffer=0A= PASS: fill it sparsely=0A= PASS: take sparse (RLE) snapshot=0A= PASS: clear memory=0A= FAIL: reload sparse (RLE) snapshot=0A= PASS: load junk snapshot=0A= FAIL: save & restore large memory snapshot - ok bad_value=0A= PASS: reset memory size to 8192=0A= PASS: map memory image from a file=0A= PASS: verify mmap memory image via read=0A= PASS: modify mmap memory image=0A= PASS: write out memory image=0A= PASS: check written memory image=0A= PASS: msync memory=0A= PASS: check msync'd memory image=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.memory/memdocs.exp = ...=0A= PASS: Documentation file (txt) for hw-memory-ram/rom-basic exists=0A= PASS: Documentation file (xml) for hw-memory-ram/rom-basic exists=0A= PASS: Documentation file seems to document hw-memory-ram/rom-basic=0A= PASS: Documentation file (txt) for hw-memory-flash-at29 exists=0A= PASS: Documentation file (xml) for hw-memory-flash-at29 exists=0A= PASS: Documentation file seems to document hw-memory-flash-at29=0A= PASS: Documentation file (txt) for hw-memory-flash-am29 exists=0A= PASS: Documentation file (xml) for hw-memory-flash-am29 exists=0A= PASS: Documentation file seems to document hw-memory-flash-am29=0A= Running ../../../../src/sid/component/testsuite/sidcomp.memory/memmonkey.ex= p ...=0A= WARNING: monkey test hw-memory-ram/rom-basic - state restore failed=0A= WARNING: monkey test hw-memory-ram/rom-basic - state restore did not preser= ve image-mmap=0A= WARNING: monkey test hw-memory-ram/rom-basic - state restore did not preser= ve image-msync=0A= UNRESOLVED: monkey test hw-memory-ram/rom-basic (30s iterations)=0A= WARNING: monkey test hw-memory-flash-at29 - state restore failed=0A= WARNING: monkey test hw-memory-flash-at29 - state restore did not preserve = image-mmap=0A= WARNING: monkey test hw-memory-flash-at29 - state restore did not preserve = image-msync=0A= UNRESOLVED: monkey test hw-memory-flash-at29 (30s iterations)=0A= WARNING: monkey test hw-memory-flash-am29 - state restore failed=0A= WARNING: monkey test hw-memory-flash-am29 - state restore did not preserve = image-mmap=0A= FAIL: monkey test hw-memory-flash-am29 - timeout after {sid::component::att= ribute_value sid-component#2 state-snapshot}=0A= UNRESOLVED: monkey test hw-memory-flash-am29 - timeout before {sid::compone= nt::find_pin sid-component#2 image-msync}=0A= UNRESOLVED: monkey test hw-memory-flash-am29 - timeout before {sid::compone= nt::find_bus sid-component#2 read-write-port}=0A= UNRESOLVED: monkey test hw-memory-flash-am29 - timeout before {sid::bus::re= ad_h4_l2 {} 9963304}=0A= FAIL: monkey test hw-memory-flash-am29 (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.mmu/arm-remap.exp .= ..=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: establish a triggerpoint for watchable state variable: remapping?=0A= PASS: set bus accessor=0A= PASS: basic attributes present=0A= PASS: take snapshot of startup state=0A= PASS: remapping? attribute is yes at initialisation=0A= PASS: switch to normal map for startup=0A= PASS: remapping? is now set to no=0A= PASS: switch back to reset map for continuation of these tests=0A= PASS: remapping? is now set to yes=0A= PASS: num-relocations is initially zero=0A= PASS: configure for two (2) relocations=0A= PASS: validate num-relocations is two (2)=0A= PASS: falling back to only one relocation gives bad_value=0A= PASS: newly generated attributes are present=0A= PASS: no extraneous attributes have been generated=0A= PASS: validate 0- attributes are all initialized=0A= PASS: validate 1- attributes are all initialized=0A= PASS: set 0- attributes=0A= PASS: set 1- attributes=0A= PASS: validate 0- attributes are set correctly=0A= PASS: validate 1- attributes are set correctly=0A= PASS: register bus is present=0A= PASS: access-port bus is present=0A= PASS: reset pin is present=0A= PASS: halt! pin is present=0A= PASS: connect accessor to a dummy bus=0A= PASS: remap around the mapped region=0A= PASS: take another state snapshot=0A= PASS: reserved register write_h4_l4 (0x10)=0A= PASS: reserved register read_h4_l4 (0x0x0)=0A= PASS: reserved register read_h4_l4 (0x0x20)=0A= PASS: reserved register read_h4_l4 (0x0x34)=0A= PASS: reset status set register write (unused)=0A= PASS: read identification register=0A= PASS: write to pause register causes halt! pin to be driven high=0A= PASS: reset status register is clear at power-up=0A= PASS: reset status register is set after a reset=0A= PASS: reset status clear register write=0A= PASS: clear reset mode memory map=0A= PASS: bus handle is invariant after switching to the normal map=0A= PASS: remapping? attribute is not in normal mode=0A= PASS: remap through the normal mapping=0A= PASS: restore initial state=0A= PASS: remapping? triggerpoint fired three times=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.mmu/mmudocs.exp ...= =0A= PASS: Documentation file (txt) for hw-remap/pause-arm/ref exists=0A= PASS: Documentation file (xml) for hw-remap/pause-arm/ref exists=0A= PASS: Documentation file seems to document hw-remap/pause-arm/ref=0A= Running ../../../../src/sid/component/testsuite/sidcomp.mmu/mmumonkey.exp .= ..=0A= PASS: monkey test hw-remap/pause-arm/ref (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.parport/parmonkey.e= xp ...=0A= PASS: monkey test hw-parport-ps/2 (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.parport/parport.exp= ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: acquire bus=0A= PASS: Reading default PR reg. val 0=0A= PASS: Reading default SR reg val 0x07=0A= PASS: Reading default COM reg val 0xE0=0A= PASS: Presence data pin 0=0A= PASS: Presence data pin 1=0A= PASS: Presence data pin 2=0A= PASS: Presence data pin 3=0A= PASS: Presence data pin 4=0A= PASS: Presence data pin 5=0A= PASS: Presence data pin 6=0A= PASS: Presence data pin 7=0A= PASS: Presence data pin 7=0A= PASS: reading PR register 0xFF=0A= PASS: op data pin 0 val=20=0A= PASS: op data pin 1 val=20=0A= PASS: op data pin 2 val=20=0A= PASS: op data pin 3 val=20=0A= PASS: op data pin 4 val=20=0A= PASS: op data pin 5 val=20=0A= PASS: op data pin 6 val=20=0A= PASS: op data pin 7 val=20=0A= PASS: op data pin 7 val=20=0A= PASS: reading PR register 0xAB=0A= PASS: op data pin 0 val=20=0A= PASS: op data pin 1 val=20=0A= PASS: op data pin 2 val=20=0A= PASS: op data pin 3 val=20=0A= PASS: op data pin 4 val=20=0A= PASS: op data pin 5 val=20=0A= PASS: op data pin 6 val=20=0A= PASS: op data pin 7 val=20=0A= PASS: op data pin 7 val=20=0A= PASS: reading PR register 0x00=0A= PASS: op data pin 0 val=20=0A= PASS: op data pin 1 val=20=0A= PASS: op data pin 2 val=20=0A= PASS: op data pin 3 val=20=0A= PASS: op data pin 4 val=20=0A= PASS: op data pin 5 val=20=0A= PASS: op data pin 6 val=20=0A= PASS: op data pin 7 val=20=0A= PASS: connected strobe pin=0A= PASS: connected autofdxt pin=0A= PASS: connected slctin pin=0A= PASS: connected init pin=0A= PASS: connected init pin=0A= PASS: reading COM register expect 255=0A= PASS: expected COM value 255=20=0A= PASS: Control op pin 0=0A= PASS: Control op pin 1=0A= PASS: Control op pin 3=0A= PASS: Control op pin 2=0A= PASS: Control op pin 2=0A= PASS: reading COM register expect 230=0A= PASS: expected COM value 230=20=0A= PASS: Control op pin 0=0A= PASS: Control op pin 1=0A= PASS: Control op pin 3=0A= PASS: Control op pin 2=0A= PASS: Control op pin 2=0A= PASS: reading COM register expect 224=0A= PASS: expected COM value 224=20=0A= PASS: Control op pin 0=0A= PASS: Control op pin 1=0A= PASS: Control op pin 3=0A= PASS: Control op pin 2=0A= PASS: get Error pin=20=0A= PASS: get SLCT pin=20=0A= PASS: get PE pin=20=0A= PASS: get ACK pin=20=0A= PASS: get Busy pin=20=0A= PASS: Inspect SR reg expect val 0xF8=0A= PASS: Inspect SR reg expect val 0xF8=0A= PASS: Inspect SR reg expect val 0xC0=0A= PASS: Inspect SR reg expect val 0xC0=0A= PASS: Inspect SR reg expect val 0x00=0A= PASS: Inspect SR reg expect val 0x00=0A= PASS: Inspect SR reg expect val 0x00=0A= PASS: Inspect SR reg expect val 0x00=0A= PASS: Save state=0A= PASS: Read mode check write to PR register=20=0A= PASS: Expecting read PR value 0x00=20=0A= PASS: op_dp(0) should be 0=20=0A= PASS: op_dp(1) should be 0=20=0A= PASS: op_dp(2) should be 0=20=0A= PASS: op_dp(3) should be 0=20=0A= PASS: op_dp(4) should be 0=20=0A= PASS: op_dp(5) should be 0=20=0A= PASS: op_dp(6) should be 0=20=0A= PASS: op_dp(7) should be 0=20=0A= PASS: Read mode PR register=20=0A= PASS: Read mode PR reg value 0xFF=20=0A= PASS: Read mode PR register=20=0A= PASS: Read mode PR reg value 0x33=20=0A= PASS: Read mode PR register=20=0A= PASS: Read mode PR reg value 0x00=20=0A= PASS: biden attribute value=20=0A= PASS: set biden to 0=0A= PASS: Read mode PR register iosel=20=0A= PASS: Read mode iosel PR reg value 0xAB=20=0A= PASS: Read mode PR register iosel=20=0A= PASS: Read mode iosel PR reg value 0x66=20=0A= PASS: Read mode PR register iosel=20=0A= PASS: Read mode iosel PR reg value 0x00=20=0A= PASS: write iosel register with value 0xAA Read Mode=0A= PASS: Read mode iosel0xAA PR register=20=0A= PASS: Read mode iosel0xAA PR reg value 0xCC=20=0A= PASS: Read mode iosel0xAA PR register=20=0A= PASS: Read mode iosel0xAA PR reg value 0x44=20=0A= PASS: Read mode iosel0xAA PR register=20=0A= PASS: Read mode iosel0xAA PR reg value 0x00=20=0A= PASS: Read mode iosel0xAA PR register=20=0A= PASS: Read mode iosel0xAA PR reg value 0xAA=20=0A= PASS: Save state=0A= PASS: states are different=0A= PASS: states are different=0A= PASS: writing PR register 0xEE iosel 0x55=0A= PASS: reading PR register iosel 0x55=0A= PASS: op data pin 0 val iosel0x55=0A= PASS: op data pin 1 val iosel0x55=0A= PASS: op data pin 2 val iosel0x55=0A= PASS: op data pin 3 val iosel0x55=0A= PASS: op data pin 4 val iosel0x55=0A= PASS: op data pin 5 val iosel0x55=0A= PASS: op data pin 6 val iosel0x55=0A= PASS: op data pin 7 val iosel0x55=0A= PASS: writing PR register 0xAA iosel 0x55=0A= PASS: reading PR register iosel 0x55=0A= PASS: op data pin 0 val iosel0x55=0A= PASS: op data pin 1 val iosel0x55=0A= PASS: op data pin 2 val iosel0x55=0A= PASS: op data pin 3 val iosel0x55=0A= PASS: op data pin 4 val iosel0x55=0A= PASS: op data pin 5 val iosel0x55=0A= PASS: op data pin 6 val iosel0x55=0A= PASS: op data pin 7 val iosel0x55=0A= PASS: writing PR register 0x00 iosel 0x55=0A= PASS: reading PR register iosel 0x55=0A= PASS: op data pin 0 val iosel0x55=0A= PASS: op data pin 1 val iosel0x55=0A= PASS: op data pin 2 val iosel0x55=0A= PASS: op data pin 3 val iosel0x55=0A= PASS: op data pin 4 val iosel0x55=0A= PASS: op data pin 5 val iosel0x55=0A= PASS: op data pin 6 val iosel0x55=0A= PASS: op data pin 7 val iosel0x55=0A= PASS: restore state=0A= PASS: test random regs after restore=0A= PASS: test random regs after restore=0A= PASS: test random regs after restore=0A= PASS: test random regs after restore=0A= PASS: get intsel attr=20=0A= PASS: set intsel val to 0=20=0A= PASS: set CON register bit 4 to 1=20=0A= PASS: read COM value expected 0xF0=0A= PASS: read COM value expected 0xF0=0A= PASS: reading intp pin=20=0A= PASS: reading SR to see ack & bit 2=20=0A= PASS: reading SR to see ack & bit 2=20=0A= PASS: reading intp pin=20=0A= PASS: reading SR to see ack & bit 2=20=0A= PASS: reading SR to see ack & bit 2=20=0A= PASS: reading intp pin=20=0A= PASS: reading SR to see ack & bit 2=20=0A= PASS: reading SR to see ack & bit 2=20=0A= PASS: set intsel value 1=0A= PASS: reading SR intsel 1=0A= PASS: reading SR intsel 1=0A= PASS: ack high intsel 1=0A= PASS: ack high intsel 1=0A= PASS: interrupt raised=0A= PASS: intp pin should remain 1=0A= PASS: intp pin should remain 1=0A= PASS: intp pin should remain 1=0A= PASS: clearing interrupt=0A= PASS: clearing interrupt=0A= PASS: clearing interrupt bit 2 should be 1=20=0A= PASS: clearing interrupt bit 2 should be 1=20=0A= PASS: Again raised interrupt=0A= PASS: disabling interrupt bit 5=0A= PASS: disabling interrupt bit 5=0A= PASS: setting intsel back to 0=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.parport/parportdocs= .exp ...=0A= PASS: Documentation file (txt) for hw-parport-ps/2 exists=0A= PASS: Documentation file (xml) for hw-parport-ps/2 exists=0A= PASS: Documentation file seems to document hw-parport-ps/2=0A= Running ../../../../src/sid/component/testsuite/sidcomp.profiling/profiling= docs.exp ...=0A= PASS: Documentation file (txt) for sw-profile-gprof exists=0A= PASS: Documentation file (xml) for sw-profile-gprof exists=0A= PASS: Documentation file seems to document sw-profile-gprof=0A= Running ../../../../src/sid/component/testsuite/sidcomp.profiling/runprof.e= xp ...=0A= UNTESTED: arm7tdmi test-prof.c (,,-mlittle-endian,--cpu=3Darm --gprof --ins= n-count=3D2037) - compile failed=0A= FAIL: profiling created gmon.out=0A= Running ../../../../src/sid/component/testsuite/sidcomp.rtc/ds1642.exp ...= =0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: read-write-port bus is present=0A= PASS: clock pin is present=0A= PASS: all attributes are present=0A= PASS: reported time since epoch is sensible=0A= PASS: establish a triggerpoint for watchable state variable: epoch-time=0A= PASS: establish a triggerpoint for watchable state variable: oscillating=0A= PASS: establish a triggerpoint for watchable state variable: write-mode=0A= PASS: save state=0A= PASS: time is incremented by an advancing clock=0A= PASS: read year attribute=0A= PASS: read month attribute=0A= PASS: read date attribute=0A= PASS: read day-of-week attribute=0A= PASS: read hour attribute=0A= PASS: read minute attribute=0A= PASS: read second attribute=0A= PASS: fill regular non-volatile memory with test bytes=0A= PASS: validate memory was written correctly=0A= PASS: out by one address is caught unmapped=0A= PASS: battery is not flat=0A= PASS: read mode does not alter epoch time=0A= PASS: write mode does not alter epoch time=0A= PASS: read year register=0A= PASS: read month register=0A= PASS: read date register=0A= PASS: read day register=0A= PASS: read hour register=0A= PASS: read minutes register=0A= PASS: read seconds register=0A= PASS: read bit stops the clock=0A= PASS: write bit stops the clock=0A= PASS: disconnect the oscillator=0A= PASS: read year register with oscillator disconnected=0A= PASS: read month register with oscillator disconnected=0A= PASS: read date register with oscillator disconnected=0A= PASS: read day register with oscillator disconnected=0A= PASS: read hour register with oscillator disconnected=0A= PASS: read minutes register with oscillator disconnected=0A= PASS: read seconds register with oscillator disconnected=0A= PASS: reconnect the oscillator=0A= PASS: reconnecting the oscillator works=0A= PASS: modify the year register=0A= PASS: modify the month register=0A= PASS: modify the date register=0A= PASS: modify the day register with an invalid value=0A= PASS: modify the day register=0A= PASS: modify the hour register=0A= PASS: modify the minute register=0A= PASS: modify the second register=0A= PASS: store data in free bits at 0x7FE=0A= PASS: store data in free bits at 0x7FD=0A= PASS: store data in free bits at 0x7FC=0A= PASS: store data in free bits at 0x7FB=0A= PASS: store data in free bits at 0x7FA=0A= PASS: epoch-time triggerpoint fired 16 times=0A= PASS: oscillating triggerpoint fired twice=0A= PASS: write-mode triggerpoint fired 37 times=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.rtc/ds1742.exp ...= =0A= PASS: sid configuration=0A= PASS: sid start=0A= PASS: read-write-port bus is present=0A= PASS: clock pin is present=0A= PASS: all attributes are present=0A= PASS: reported time since epoch is sensible=0A= PASS: establish a triggerpoint for watchable state variable: epoch-time=0A= PASS: establish a triggerpoint for watchable state variable: oscillating=0A= PASS: establish a triggerpoint for watchable state variable: write-mode=0A= PASS: save state=0A= PASS: time is incremented by an advancing clock=0A= PASS: read century attribute=0A= PASS: read year attribute=0A= PASS: read month attribute=0A= PASS: read date attribute=0A= PASS: read day-of-week attribute=0A= PASS: read hour attribute=0A= PASS: read minute attribute=0A= PASS: read second attribute=0A= PASS: fill regular non-volatile memory with test bytes=0A= PASS: validate memory was written correctly=0A= PASS: out by one address is caught unmapped=0A= PASS: battery is not flat=0A= PASS: read mode does not alter epoch time=0A= PASS: write mode does not alter epoch time=0A= PASS: read year register=0A= PASS: read month register=0A= PASS: read date register=0A= PASS: read day register=0A= PASS: read hour register=0A= PASS: read minutes register=0A= PASS: read seconds register=0A= PASS: read bit stops the clock=0A= PASS: write bit stops the clock=0A= PASS: disconnect the oscillator=0A= PASS: read year register with oscillator disconnected=0A= PASS: read month register with oscillator disconnected=0A= PASS: read date register with oscillator disconnected=0A= PASS: read day register with oscillator disconnected=0A= PASS: read hour register with oscillator disconnected=0A= PASS: read minutes register with oscillator disconnected=0A= PASS: read seconds register with oscillator disconnected=0A= PASS: reconnect the oscillator=0A= PASS: reconnecting the oscillator works=0A= PASS: modify the year register=0A= PASS: modify the month register=0A= PASS: modify the date register=0A= PASS: modify the day register with an invalid value=0A= PASS: modify the day register=0A= PASS: modify the hour register=0A= PASS: modify the minute register=0A= PASS: modify the second register=0A= PASS: modify the century register=0A= PASS: Restore state=0A= PASS: time is incremented by an advancing clock=0A= PASS: read century attribute=0A= PASS: read year attribute=0A= PASS: read month attribute=0A= PASS: read date attribute=0A= PASS: read day-of-week attribute=0A= PASS: read hour attribute=0A= PASS: read minute attribute=0A= PASS: read second attribute=0A= PASS: fill regular non-volatile memory with test bytes=0A= PASS: validate memory was written correctly=0A= PASS: out by one address is caught unmapped=0A= PASS: battery is not flat=0A= PASS: read mode does not alter epoch time=0A= PASS: write mode does not alter epoch time=0A= PASS: read year register=0A= PASS: read month register=0A= PASS: read date register=0A= PASS: read day register=0A= PASS: read hour register=0A= PASS: read minutes register=0A= PASS: read seconds register=0A= PASS: read bit stops the clock=0A= PASS: write bit stops the clock=0A= PASS: disconnect the oscillator=0A= PASS: read year register with oscillator disconnected=0A= PASS: read month register with oscillator disconnected=0A= PASS: read date register with oscillator disconnected=0A= PASS: read day register with oscillator disconnected=0A= PASS: read hour register with oscillator disconnected=0A= PASS: read minutes register with oscillator disconnected=0A= PASS: read seconds register with oscillator disconnected=0A= PASS: reconnect the oscillator=0A= PASS: reconnecting the oscillator works=0A= PASS: modify the year register=0A= PASS: modify the month register=0A= PASS: modify the date register=0A= PASS: modify the day register with an invalid value=0A= PASS: modify the day register=0A= PASS: modify the hour register=0A= PASS: modify the minute register=0A= PASS: modify the second register=0A= PASS: modify the century register=0A= PASS: store data in free bits at 0x7FE=0A= PASS: store data in free bits at 0x7FD=0A= PASS: store data in free bits at 0x7FC=0A= PASS: store data in free bits at 0x7FB=0A= PASS: store data in free bits at 0x7FA=0A= PASS: epoch-time triggerpoint fired 16 times=0A= PASS: oscillating triggerpoint fired twice=0A= PASS: write-mode triggerpoint fired 37 times=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.rtc/rtcdocs.exp ...= =0A= PASS: Documentation file (txt) for hw-rtc-ds1642 exists=0A= PASS: Documentation file (xml) for hw-rtc-ds1642 exists=0A= PASS: Documentation file seems to document hw-rtc-ds1642=0A= PASS: Documentation file (txt) for hw-rtc-ds1742 exists=0A= PASS: Documentation file (xml) for hw-rtc-ds1742 exists=0A= PASS: Documentation file seems to document hw-rtc-ds1742=0A= PASS: Documentation file (txt) for hw-rtc-sid exists=0A= PASS: Documentation file (xml) for hw-rtc-sid exists=0A= PASS: Documentation file seems to document hw-rtc-sid=0A= PASS: Documentation file (txt) for hw-visual-clock exists=0A= PASS: Documentation file (xml) for hw-visual-clock exists=0A= PASS: Documentation file seems to document hw-visual-clock=0A= Running ../../../../src/sid/component/testsuite/sidcomp.rtc/rtcmonkey.exp .= ..=0A= PASS: monkey test hw-rtc-ds1642 (30s iterations)=0A= PASS: monkey test hw-rtc-ds1742 (30s iterations)=0A= PASS: monkey test hw-rtc-sid (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.sched/schedbase.exp= ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: attribute list=0A= PASS: check num-clients=3D0=0A= PASS: set num-clients=3D2=0A= PASS: attribute list proper after growth=0A= PASS: reset num-clients=3D1=0A= PASS: set out-of-range num-clients=0A= PASS: check num-clients=3D1=0A= PASS: attribute list proper after shrinkage=0A= PASS: one-shot event=0A= PASS: multiple interleaved regular subscriptions=0A= PASS: multiple interleaved regular subscriptions with scaling=0A= PASS: save state snapshot=0A= PASS: cancel some regular events; exercise yielding=0A= PASS: cancel last regular event=0A= PASS: save state snapshot before restore=0A= PASS: restore state snapshot=0A= PASS: save state snapshot after restore=0A= PASS: compare original and post-restore state snapshots=0A= PASS: cancel some regular events (after restore)=0A= PASS: cancel last regular event (after restore)=0A= PASS: invalid scales=0A= PASS: tolerate teeny scales=0A= PASS: try save/restore with num_clients=3D10=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.sched/scheddocs.exp= ...=0A= PASS: Documentation file (txt) for sid-sched-host exists=0A= PASS: Documentation file (xml) for sid-sched-host exists=0A= PASS: Documentation file seems to document sid-sched-host=0A= PASS: Documentation file (txt) for sid-sched-host-accurate exists=0A= PASS: Documentation file (xml) for sid-sched-host-accurate exists=0A= PASS: Documentation file seems to document sid-sched-host-accurate=0A= PASS: Documentation file (txt) for sid-sched-sim exists=0A= PASS: Documentation file (xml) for sid-sched-sim exists=0A= PASS: Documentation file seems to document sid-sched-sim=0A= Running ../../../../src/sid/component/testsuite/sidcomp.sched/schedhost.exp= ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: host time regular events=0A= PASS: idle-mode host time regular events=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.sched/schedhost2.ex= p ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: host time regular events=0A= PASS: idle-mode host time regular events=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.sched/schedmonkey.e= xp ...=0A= PASS: monkey test sid-sched-sim (30s iterations)=0A= PASS: monkey test sid-sched-host-accurate (30s iterations)=0A= PASS: monkey test sid-sched-host (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.timers/timerbase.ex= p ...=0A= PASS: sid configuration=0A= PASS: sid startup=0A= PASS: establish a triggerpoint for watchable state variable: enabled=0A= PASS: establish a triggerpoint for watchable state variable: mode=0A= PASS: establish a triggerpoint for watchable state variable: prescale=0A= PASS: establish a triggerpoint for watchable state variable: load-value=0A= PASS: establish a triggerpoint for watchable state variable: counter=0A= PASS: attribute list=0A= PASS: reserved register write_h4_l4 (0x04)=0A= PASS: reserved register read_h4_l4 (0x04)=0A= PASS: reserved register write_h4_l4 (0x10)=0A= PASS: reserved register read_h4_l4 (0x010)=0A= PASS: set / retrieve a load value (byte)=0A= PASS: save state=0A= PASS: set / retrieve a load value (half-word)=0A= PASS: Re save state=0A= PASS: restore state=0A= PASS: Re Re save state=0A= PASS: set / retrieve a load value (word)=0A= PASS: retrieve timer value (word)=0A= PASS: clear interrupts=0A= PASS: get control word=0A= PASS: turn timer on=0A= PASS: tick presence of clock pin=0A= PASS: tick timer for almost 0x0C steps =3D 0xBF ticks=0A= PASS: tick timer for final tick=0A= PASS: clear interrupt=0A= PASS: enabled triggerpoint fired twice=0A= PASS: mode triggerpoint fired twice=0A= PASS: prescale triggerpoint fired twice=0A= PASS: load-value triggerpoint fired four times=0A= PASS: counter triggerpoint fired 16 times=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.timers/timerdocs.ex= p ...=0A= PASS: Documentation file (txt) for hw-timer-arm/ref-nosched exists=0A= FAIL: Documentation file (xml) for hw-timer-arm/ref-nosched is missing=0A= FAIL: Documentation file does not seem to document hw-timer-arm/ref-nosched= =0A= PASS: Documentation file (txt) for hw-timer-arm/ref-sched exists=0A= FAIL: Documentation file (xml) for hw-timer-arm/ref-sched is missing=0A= FAIL: Documentation file does not seem to document hw-timer-arm/ref-sched= =0A= Running ../../../../src/sid/component/testsuite/sidcomp.timers/timermonkey.= exp ...=0A= PASS: monkey test hw-timer-arm/ref-nosched (30s iterations)=0A= PASS: monkey test hw-timer-arm/ref-sched (30s iterations)=0A= Running ../../../../src/sid/component/testsuite/sidcomp.timers/timersched.e= xp ...=0A= PASS: sid configuration w/ scheduler=0A= PASS: sid startup=0A= PASS: test presence of scheduler component=0A= PASS: attribute list=0A= PASS: reserved register write_h4_l4 (0x04)=0A= PASS: reserved register read_h4_l4 (0x04)=0A= PASS: reserved register write_h4_l4 (0x10)=0A= PASS: reserved register read_h4_l4 (0x010)=0A= PASS: set / retrieve a load value (byte)=0A= PASS: set / retrieve a load value (half-word)=0A= PASS: set / retrieve a load value (word)=0A= PASS: retrieve timer value (word)=0A= PASS: clear interrupts=0A= PASS: get control word=0A= PASS: turn timer on=0A= PASS: tick presence of scheduler clock pin=0A= PASS: tick timer for almost 0x0C steps =3D 0xB scheduler ticks=0A= PASS: tick timer for final tick=0A= PASS: clear interrupt=0A= PASS: sid stop=0A= Running ../../../../src/sid/component/testsuite/sidcomp.uart/uartdocs.exp .= ..=0A= PASS: Documentation file (txt) for hw-uart-ns16550 exists=0A= PASS: Documentation file (xml) for hw-uart-ns16550 exists=0A= PASS: Documentation file seems to document hw-uart-ns16550=0A= =0A= =3D=3D=3D sidcomp Summary =3D=3D=3D=0A= =0A= # of expected passes 2017=0A= # of unexpected failures 43=0A= # of unresolved testcases 9=0A= # of untested testcases 119=0A= sidcomp test 0.1=0A= =0A= ------=_NextPart_000_0007_01C24F4E.99BDEE80--