From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8990 invoked by alias); 3 Sep 2002 11:29:10 -0000 Mailing-List: contact cgen-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sources.redhat.com Received: (qmail 8952 invoked from network); 3 Sep 2002 11:29:07 -0000 Received: from unknown (HELO www.jennic.com) (213.143.5.74) by sources.redhat.com with SMTP; 3 Sep 2002 11:29:07 -0000 Received: from jensun01.jennic.com (jensun01.jennic.com [99.99.98.151]) by www.jennic.com (8.9.3/8.9.3) with ESMTP id LAA04773; Tue, 3 Sep 2002 11:54:31 +0100 Received: from jenpc60 (jenpc60 [99.99.98.60]) by jensun01.jennic.com (8.9.3/8.9.3) with SMTP id MAA04391; Tue, 3 Sep 2002 12:29:06 +0100 (BST) From: "Robert Cragie" To: , Subject: RE: [patch] Additional insn support for ARM7T Date: Tue, 03 Sep 2002 04:29:00 -0000 Message-ID: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0003_01C25345.7E2FB5E0" X-Priority: 3 (Normal) X-MSMail-Priority: Normal In-Reply-To: X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Importance: Normal X-SW-Source: 2002-q3/txt/msg00041.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_0003_01C25345.7E2FB5E0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-length: 1202 I had trouble extracting the patch from the mail. Here is it is an an attachment. To apply: cd /src/cgen/cpu patch -p0 < arm7.cpu.patch cd /build/sid/component/cgen-cpu/arm7t make cgen-all cd ../../../ make all install where is your SID home directory. Robert Cragie, Design Engineer _______________________________________________________________ Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK http://www.jennic.com Tel: +44 (0) 114 281 2655 > -----Original Message----- > From: sid-owner@sources.redhat.com > [mailto:sid-owner@sources.redhat.com]On Behalf Of Robert Cragie > Sent: 29 August 2002 11:24 > To: sid@sources.redhat.com; cgen@sources.redhat.com > Subject: [patch] Additional insn support for ARM7T > > > Whilst trying to get eCos to run on SID, I realised it was > failing due to a > LDMIA instruction not being emulated in the CPU simulator. Here is a patch > to complete the combinations of LDM/STM instructions which are missing in > CGEN for the ARM7. I have a feeling that it could be implemented more > efficiently, but I am somewhat a newbie to Scheme, and also to > contributing > patches in the GNU manner, so please bear with me. [snip] ------=_NextPart_000_0003_01C25345.7E2FB5E0 Content-Type: application/octet-stream; name="arm7.cpu.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="arm7.cpu.patch" Content-length: 25266 Index: arm7.cpu=0A= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A= RCS file: /cvs/src/src/cgen/cpu/arm7.cpu,v=0A= retrieving revision 1.1=0A= diff -c -p -r1.1 arm7.cpu=0A= *** arm7.cpu 5 Jul 2001 12:45:47 -0000 1.1=0A= --- arm7.cpu 3 Sep 2002 11:13:39 -0000=0A= ***************=0A= *** 1453,1458 ****=0A= --- 1453,1473 ----=0A= (set addr (sub addr 4)))=0A= )=0A= =20=20=0A= + (define-pmacro (ldmda-sw-action bit-num)=0A= + (sequence ()=0A= + (if (and reglist (sll 1 15))=0A= + (set (reg WI h-gr bit-num) (mem WI addr))=0A= + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr)))=0A= + (set addr (sub addr 4)))=0A= + )=0A= +=20=0A= + (define-pmacro (ldmda-sw-action-r15 ignored)=0A= + (sequence ()=0A= + (set pc (mem WI addr))=0A= + (set addr (sub addr 4))=0A= + (set (reg h-cpsr) (reg h-spsr)))=0A= + )=0A= +=20=0A= (dnai ldmda "Load multiple registers (postindex, decrement)"=0A= ()=0A= "FIXME"=0A= ***************=0A= *** 1479,1484 ****=0A= --- 1494,1525 ----=0A= )=0A= )=0A= =20=20=0A= + (dnai ldmda-sw "Load multiple registers (postindex, decrement, switch)"= =0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1)=0A= + (f-write-back? 0) (f-load? 1) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 15 ldmda-sw-action-r15)=0A= + (multi-action 14 ldmda-sw-action)=0A= + (multi-action 13 ldmda-sw-action)=0A= + (multi-action 12 ldmda-sw-action)=0A= + (multi-action 11 ldmda-sw-action)=0A= + (multi-action 10 ldmda-sw-action)=0A= + (multi-action 9 ldmda-sw-action)=0A= + (multi-action 8 ldmda-sw-action)=0A= + (multi-action 7 ldmda-action)=0A= + (multi-action 6 ldmda-action)=0A= + (multi-action 5 ldmda-action)=0A= + (multi-action 4 ldmda-action)=0A= + (multi-action 3 ldmda-action)=0A= + (multi-action 2 ldmda-action)=0A= + (multi-action 1 ldmda-action)=0A= + (multi-action 0 ldmda-action)=0A= + )=0A= + )=0A= +=20=0A= (dnai ldmda-wb "Load multiple registers (postindex, decrement, writeback)= "=0A= ()=0A= "FIXME"=0A= ***************=0A= *** 1505,1510 ****=0A= --- 1546,1577 ----=0A= (set rn addr))=0A= )=0A= =20=20=0A= + (dnai ldmda-sw-wb "Load multiple registers (postindex, decrement, switch,= writeback)"=0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1)=0A= + (f-write-back? 1) (f-load? 1) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 15 ldmda-sw-action-r15)=0A= + (multi-action 14 ldmda-sw-action)=0A= + (multi-action 13 ldmda-sw-action)=0A= + (multi-action 12 ldmda-sw-action)=0A= + (multi-action 11 ldmda-sw-action)=0A= + (multi-action 10 ldmda-sw-action)=0A= + (multi-action 9 ldmda-sw-action)=0A= + (multi-action 8 ldmda-sw-action)=0A= + (multi-action 7 ldmda-action)=0A= + (multi-action 6 ldmda-action)=0A= + (multi-action 5 ldmda-action)=0A= + (multi-action 4 ldmda-action)=0A= + (multi-action 3 ldmda-action)=0A= + (multi-action 2 ldmda-action)=0A= + (multi-action 1 ldmda-action)=0A= + (multi-action 0 ldmda-action)=0A= + (set rn addr))=0A= + )=0A= +=20=0A= (define-pmacro (ldmib-action bit-num)=0A= (sequence ()=0A= (set addr (add addr 4))=0A= ***************=0A= *** 1517,1522 ****=0A= --- 1584,1604 ----=0A= (set pc (mem WI addr)))=0A= )=0A= =20=20=0A= + (define-pmacro (ldmib-sw-action bit-num)=0A= + (sequence ()=0A= + (set addr (add addr 4))=0A= + (if (and reglist (sll 1 15))=0A= + (set (reg WI h-gr bit-num) (mem WI addr))=0A= + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr))))=0A= + )=0A= +=20=0A= + (define-pmacro (ldmib-sw-action-r15 ignored)=0A= + (sequence ()=0A= + (set addr (add addr 4))=0A= + (set pc (mem WI addr))=0A= + (set (reg h-cpsr) (reg h-spsr)))=0A= + )=0A= +=20=0A= (dnai ldmib "Load multiple register (preindex, increment)"=0A= ()=0A= "FIXME"=0A= ***************=0A= *** 1542,1547 ****=0A= --- 1624,1654 ----=0A= (multi-action 15 ldmib-action-r15))=0A= )=0A= =20=20=0A= + (dnai ldmib-sw "Load multiple register (preindex, increment, switch)"=0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1)=0A= + (f-write-back? 0) (f-load? 1) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 0 ldmib-action)=0A= + (multi-action 1 ldmib-action)=0A= + (multi-action 2 ldmib-action)=0A= + (multi-action 3 ldmib-action)=0A= + (multi-action 4 ldmib-action)=0A= + (multi-action 5 ldmib-action)=0A= + (multi-action 6 ldmib-action)=0A= + (multi-action 7 ldmib-action)=0A= + (multi-action 8 ldmib-sw-action)=0A= + (multi-action 9 ldmib-sw-action)=0A= + (multi-action 10 ldmib-sw-action)=0A= + (multi-action 11 ldmib-sw-action)=0A= + (multi-action 12 ldmib-sw-action)=0A= + (multi-action 13 ldmib-sw-action)=0A= + (multi-action 14 ldmib-sw-action)=0A= + (multi-action 15 ldmib-sw-action-r15))=0A= + )=0A= +=20=0A= (dnai ldmib-wb "Load multiple registers (preindex, increment, writeback)"= =0A= ()=0A= "FIXME"=0A= ***************=0A= *** 1568,1573 ****=0A= --- 1675,1706 ----=0A= (set rn addr))=0A= )=0A= =20=20=0A= + (dnai ldmib-sw-wb "Load multiple registers (preindex, increment, switch, = writeback)"=0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1)=0A= + (f-write-back? 1) (f-load? 1) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 0 ldmib-action)=0A= + (multi-action 1 ldmib-action)=0A= + (multi-action 2 ldmib-action)=0A= + (multi-action 3 ldmib-action)=0A= + (multi-action 4 ldmib-action)=0A= + (multi-action 5 ldmib-action)=0A= + (multi-action 6 ldmib-action)=0A= + (multi-action 7 ldmib-action)=0A= + (multi-action 8 ldmib-sw-action)=0A= + (multi-action 9 ldmib-sw-action)=0A= + (multi-action 10 ldmib-sw-action)=0A= + (multi-action 11 ldmib-sw-action)=0A= + (multi-action 12 ldmib-sw-action)=0A= + (multi-action 13 ldmib-sw-action)=0A= + (multi-action 14 ldmib-sw-action)=0A= + (multi-action 15 ldmib-sw-action-r15)=0A= + (set rn addr))=0A= + )=0A= +=20=0A= (define-pmacro (ldmia-action bit-num)=0A= (sequence ()=0A= (set (reg WI h-gr bit-num) (mem WI addr))=0A= ***************=0A= *** 1580,1585 ****=0A= --- 1713,1733 ----=0A= (set addr (add addr 4)))=0A= )=0A= =20=20=0A= + (define-pmacro (ldmia-sw-action bit-num)=0A= + (sequence ()=0A= + (if (and reglist (sll 1 15))=0A= + (set (reg WI h-gr bit-num) (mem WI addr))=0A= + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr)))=0A= + (set addr (add addr 4)))=0A= + )=0A= +=20=0A= + (define-pmacro (ldmia-sw-action-r15 ignored)=0A= + (sequence ()=0A= + (set pc (mem WI addr))=0A= + (set addr (add addr 4))=0A= + (set (reg h-cpsr) (reg h-spsr)))=0A= + )=0A= +=20=0A= (dnai ldmia "Load multiple registers (postindex, increment)"=0A= ()=0A= "FIXME"=0A= ***************=0A= *** 1605,1610 ****=0A= --- 1753,1783 ----=0A= (multi-action 15 ldmia-action-r15))=0A= )=0A= =20=20=0A= + (dnai ldmia-sw "Load multiple registers (postindex, increment, switch)"= =0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1)=0A= + (f-write-back? 0) (f-load? 1) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 0 ldmia-action)=0A= + (multi-action 1 ldmia-action)=0A= + (multi-action 2 ldmia-action)=0A= + (multi-action 3 ldmia-action)=0A= + (multi-action 4 ldmia-action)=0A= + (multi-action 5 ldmia-action)=0A= + (multi-action 6 ldmia-action)=0A= + (multi-action 7 ldmia-action)=0A= + (multi-action 8 ldmia-sw-action)=0A= + (multi-action 9 ldmia-sw-action)=0A= + (multi-action 10 ldmia-sw-action)=0A= + (multi-action 11 ldmia-sw-action)=0A= + (multi-action 12 ldmia-sw-action)=0A= + (multi-action 13 ldmia-sw-action)=0A= + (multi-action 14 ldmia-sw-action)=0A= + (multi-action 15 ldmia-sw-action-r15))=0A= + )=0A= +=20=0A= (dnai ldmia-wb "Load multiple registers (postindex, increment, writeback)= "=0A= ()=0A= "FIXME"=0A= ***************=0A= *** 1631,1636 ****=0A= --- 1804,1835 ----=0A= (set rn addr))=0A= )=0A= =20=20=0A= + (dnai ldmia-sw-wb "Load multiple registers (postindex, increment, switch,= writeback)"=0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1)=0A= + (f-write-back? 1) (f-load? 1) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 0 ldmia-action)=0A= + (multi-action 1 ldmia-action)=0A= + (multi-action 2 ldmia-action)=0A= + (multi-action 3 ldmia-action)=0A= + (multi-action 4 ldmia-action)=0A= + (multi-action 5 ldmia-action)=0A= + (multi-action 6 ldmia-action)=0A= + (multi-action 7 ldmia-action)=0A= + (multi-action 8 ldmia-sw-action)=0A= + (multi-action 9 ldmia-sw-action)=0A= + (multi-action 10 ldmia-sw-action)=0A= + (multi-action 11 ldmia-sw-action)=0A= + (multi-action 12 ldmia-sw-action)=0A= + (multi-action 13 ldmia-sw-action)=0A= + (multi-action 14 ldmia-sw-action)=0A= + (multi-action 15 ldmia-sw-action-r15)=0A= + (set rn addr))=0A= + )=0A= +=20=0A= (define-pmacro (ldmdb-action bit-num)=0A= (sequence ()=0A= (set addr (sub addr 4))=0A= ***************=0A= *** 1643,1648 ****=0A= --- 1842,1862 ----=0A= (set pc (mem WI addr)))=0A= )=0A= =20=20=0A= + (define-pmacro (ldmdb-sw-action bit-num)=0A= + (sequence ()=0A= + (set addr (sub addr 4))=0A= + (if (and reglist (sll 1 15))=0A= + (set (reg WI h-gr bit-num) (mem WI addr))=0A= + (set (reg WI h-gr-usr (sub bit-num 8)) (mem WI addr))))=0A= + )=0A= +=20=0A= + (define-pmacro (ldmdb-sw-action-r15 ignored)=0A= + (sequence ()=0A= + (set addr (sub addr 4))=0A= + (set pc (mem WI addr))=0A= + (set (reg h-cpsr) (reg h-spsr)))=0A= + )=0A= +=20=0A= (dnai ldmdb "Load multiple registers (preindex, decrement)"=20=0A= ()=0A= "ldm$cond .."=0A= ***************=0A= *** 1668,1673 ****=0A= --- 1882,1912 ----=0A= (multi-action 0 ldmdb-action))=0A= )=0A= =20=20=0A= + (dnai ldmdb-sw "Load multiple registers (preindex, decrement, switch)"=20= =0A= + ()=0A= + "ldm$cond .."=0A= + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1)=0A= + (f-write-back? 0) (f-load? 1) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 15 ldmdb-sw-action-r15)=0A= + (multi-action 14 ldmdb-sw-action)=0A= + (multi-action 13 ldmdb-sw-action)=0A= + (multi-action 12 ldmdb-sw-action)=0A= + (multi-action 11 ldmdb-sw-action)=0A= + (multi-action 10 ldmdb-sw-action)=0A= + (multi-action 9 ldmdb-sw-action)=0A= + (multi-action 8 ldmdb-sw-action)=0A= + (multi-action 7 ldmdb-action)=0A= + (multi-action 6 ldmdb-action)=0A= + (multi-action 5 ldmdb-action)=0A= + (multi-action 4 ldmdb-action)=0A= + (multi-action 3 ldmdb-action)=0A= + (multi-action 2 ldmdb-action)=0A= + (multi-action 1 ldmdb-action)=0A= + (multi-action 0 ldmdb-action))=0A= + )=0A= +=20=0A= (dnai ldmdb-wb "Load multiple registers (preindex, decrement, writeback)"= =0A= ()=0A= "FIXME"=0A= ***************=0A= *** 1694,1705 ****=0A= --- 1933,1978 ----=0A= (set rn addr))=0A= )=0A= =20=20=0A= + (dnai ldmdb-sw-wb "Load multiple registers (preindex, decrement, switch, = writeback)"=0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1)=0A= + (f-write-back? 1) (f-load? 1) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 15 ldmdb-sw-action-r15)=0A= + (multi-action 14 ldmdb-sw-action)=0A= + (multi-action 13 ldmdb-sw-action)=0A= + (multi-action 12 ldmdb-sw-action)=0A= + (multi-action 11 ldmdb-sw-action)=0A= + (multi-action 10 ldmdb-sw-action)=0A= + (multi-action 9 ldmdb-sw-action)=0A= + (multi-action 8 ldmdb-sw-action)=0A= + (multi-action 7 ldmdb-action)=0A= + (multi-action 6 ldmdb-action)=0A= + (multi-action 5 ldmdb-action)=0A= + (multi-action 4 ldmdb-action)=0A= + (multi-action 3 ldmdb-action)=0A= + (multi-action 2 ldmdb-action)=0A= + (multi-action 1 ldmdb-action)=0A= + (multi-action 0 ldmdb-action)=0A= + (set rn addr))=0A= + )=0A= +=20=0A= (define-pmacro (stmdb-action bit-num)=0A= (sequence ()=0A= (set addr (sub addr 4))=0A= (set (mem WI addr) (reg WI h-gr bit-num)))=0A= )=0A= =20=20=0A= + (define-pmacro (stmdb-sw-action bit-num)=0A= + (sequence ()=0A= + (set addr (sub addr 4))=0A= + (if (and reglist (sll 1 15))=0A= + (set (mem WI addr) (reg WI h-gr bit-num))=0A= + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8)))))=0A= + )=0A= +=20=0A= (define-pmacro (stmdb-action-r15 ignore)=0A= (sequence ()=0A= (set addr (sub addr 4))=0A= ***************=0A= *** 1731,1736 ****=0A= --- 2004,2034 ----=0A= (multi-action 0 stmdb-action))=0A= )=0A= =20=20=0A= + (dnai stmdb-sw "Store multiple registers (preindex, decrement, switch)"= =0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1)=0A= + (f-write-back? 0) (f-load? 0) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 15 stmdb-action-r15)=0A= + (multi-action 14 stmdb-sw-action)=0A= + (multi-action 13 stmdb-sw-action)=0A= + (multi-action 12 stmdb-sw-action)=0A= + (multi-action 11 stmdb-sw-action)=0A= + (multi-action 10 stmdb-sw-action)=0A= + (multi-action 9 stmdb-sw-action)=0A= + (multi-action 8 stmdb-sw-action)=0A= + (multi-action 7 stmdb-action)=0A= + (multi-action 6 stmdb-action)=0A= + (multi-action 5 stmdb-action)=0A= + (multi-action 4 stmdb-action)=0A= + (multi-action 3 stmdb-action)=0A= + (multi-action 2 stmdb-action)=0A= + (multi-action 1 stmdb-action)=0A= + (multi-action 0 stmdb-action))=0A= + )=0A= +=20=0A= (dnai stmdb-wb "Store multiple registers (preindex, decrement, writeback)= "=0A= ()=0A= "FIXME"=0A= ***************=0A= *** 1757,1768 ****=0A= --- 2055,2100 ----=0A= (set rn addr))=0A= )=0A= =20=20=0A= + (dnai stmdb-sw-wb "Store multiple registers (preindex, decrement, switch,= writeback)"=0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 0) (f-load-psr? 1)=0A= + (f-write-back? 1) (f-load? 0) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 15 stmdb-action-r15)=0A= + (multi-action 14 stmdb-sw-action)=0A= + (multi-action 13 stmdb-sw-action)=0A= + (multi-action 12 stmdb-sw-action)=0A= + (multi-action 11 stmdb-sw-action)=0A= + (multi-action 10 stmdb-sw-action)=0A= + (multi-action 9 stmdb-sw-action)=0A= + (multi-action 8 stmdb-sw-action)=0A= + (multi-action 7 stmdb-action)=0A= + (multi-action 6 stmdb-action)=0A= + (multi-action 5 stmdb-action)=0A= + (multi-action 4 stmdb-action)=0A= + (multi-action 3 stmdb-action)=0A= + (multi-action 2 stmdb-action)=0A= + (multi-action 1 stmdb-action)=0A= + (multi-action 0 stmdb-action)=0A= + (set rn addr))=0A= + )=0A= +=20=0A= (define-pmacro (stmib-action bit-num)=0A= (sequence ()=0A= (set addr (add addr 4))=0A= (set (mem WI addr) (reg WI h-gr bit-num)))=0A= )=0A= =20=20=0A= + (define-pmacro (stmib-sw-action bit-num)=0A= + (sequence ()=0A= + (set addr (add addr 4))=0A= + (if (and reglist (sll 1 15))=0A= + (set (mem WI addr) (reg WI h-gr bit-num))=0A= + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8)))))=0A= + )=0A= +=20=0A= (define-pmacro (stmib-action-r15 ignore)=0A= (sequence ()=0A= (set addr (add addr 4))=0A= ***************=0A= *** 1794,1799 ****=0A= --- 2126,2156 ----=0A= (multi-action 15 stmib-action-r15))=0A= )=0A= =20=20=0A= + (dnai stmib-sw "Store multiple registers (preindex, increment, switch)"= =0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1)=0A= + (f-write-back? 0) (f-load? 0) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 0 stmib-action)=0A= + (multi-action 1 stmib-action)=0A= + (multi-action 2 stmib-action)=0A= + (multi-action 3 stmib-action)=0A= + (multi-action 4 stmib-action)=0A= + (multi-action 5 stmib-action)=0A= + (multi-action 6 stmib-action)=0A= + (multi-action 7 stmib-action)=0A= + (multi-action 8 stmib-sw-action)=0A= + (multi-action 9 stmib-sw-action)=0A= + (multi-action 10 stmib-sw-action)=0A= + (multi-action 11 stmib-sw-action)=0A= + (multi-action 12 stmib-sw-action)=0A= + (multi-action 13 stmib-sw-action)=0A= + (multi-action 14 stmib-sw-action)=0A= + (multi-action 15 stmib-action-r15))=0A= + )=0A= +=20=0A= (dnai stmib-wb "Store multiple registers (preindex, increment, writeback)= "=0A= ()=0A= "FIXME"=0A= ***************=0A= *** 1820,1831 ****=0A= --- 2177,2222 ----=0A= (set rn addr))=0A= )=0A= =20=20=0A= + (dnai stmib-sw-wb "Store multiple registers (preindex, increment, switch,= writeback)"=0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 1) (f-up-down 1) (f-load-psr? 1)=0A= + (f-write-back? 1) (f-load? 0) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 0 stmib-action)=0A= + (multi-action 1 stmib-action)=0A= + (multi-action 2 stmib-action)=0A= + (multi-action 3 stmib-action)=0A= + (multi-action 4 stmib-action)=0A= + (multi-action 5 stmib-action)=0A= + (multi-action 6 stmib-action)=0A= + (multi-action 7 stmib-action)=0A= + (multi-action 8 stmib-sw-action)=0A= + (multi-action 9 stmib-sw-action)=0A= + (multi-action 10 stmib-sw-action)=0A= + (multi-action 11 stmib-sw-action)=0A= + (multi-action 12 stmib-sw-action)=0A= + (multi-action 13 stmib-sw-action)=0A= + (multi-action 14 stmib-sw-action)=0A= + (multi-action 15 stmib-action-r15)=0A= + (set rn addr))=0A= + )=0A= +=20=0A= (define-pmacro (stmia-action bit-num)=0A= (sequence ()=0A= (set (mem WI addr) (reg WI h-gr bit-num))=0A= (set addr (add addr 4)))=0A= )=0A= =20=20=0A= + (define-pmacro (stmia-sw-action bit-num)=0A= + (sequence ()=0A= + (if (and reglist (sll 1 15))=0A= + (set (mem WI addr) (reg WI h-gr bit-num))=0A= + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8))))=0A= + (set addr (add addr 4)))=0A= + )=0A= +=20=0A= (define-pmacro (stmia-action-r15 ignore)=0A= (sequence ()=0A= (set (mem WI addr) (add (reg WI h-gr 15) 4))=0A= ***************=0A= *** 1857,1862 ****=0A= --- 2248,2278 ----=0A= (multi-action 15 stmia-action-r15))=0A= )=0A= =20=20=0A= + (dnai stmia-sw "Store multiple registers (postindex, increment, switch)"= =0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1)=0A= + (f-write-back? 0) (f-load? 0) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 0 stmia-action)=0A= + (multi-action 1 stmia-action)=0A= + (multi-action 2 stmia-action)=0A= + (multi-action 3 stmia-action)=0A= + (multi-action 4 stmia-action)=0A= + (multi-action 5 stmia-action)=0A= + (multi-action 6 stmia-action)=0A= + (multi-action 7 stmia-action)=0A= + (multi-action 8 stmia-sw-action)=0A= + (multi-action 9 stmia-sw-action)=0A= + (multi-action 10 stmia-sw-action)=0A= + (multi-action 11 stmia-sw-action)=0A= + (multi-action 12 stmia-sw-action)=0A= + (multi-action 13 stmia-sw-action)=0A= + (multi-action 14 stmia-sw-action)=0A= + (multi-action 15 stmia-action-r15))=0A= + )=0A= +=20=0A= (dnai stmia-wb "Store multiple registers (postindex, increment, writeback= )"=0A= ()=0A= "FIXME"=0A= ***************=0A= *** 1883,1894 ****=0A= --- 2299,2344 ----=0A= (set rn addr))=0A= )=0A= =20=20=0A= + (dnai stmia-sw-wb "Store multiple registers (postindex, increment, switch= , writeback)"=0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 1) (f-load-psr? 1)=0A= + (f-write-back? 1) (f-load? 0) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 0 stmia-action)=0A= + (multi-action 1 stmia-action)=0A= + (multi-action 2 stmia-action)=0A= + (multi-action 3 stmia-action)=0A= + (multi-action 4 stmia-action)=0A= + (multi-action 5 stmia-action)=0A= + (multi-action 6 stmia-action)=0A= + (multi-action 7 stmia-action)=0A= + (multi-action 8 stmia-sw-action)=0A= + (multi-action 9 stmia-sw-action)=0A= + (multi-action 10 stmia-sw-action)=0A= + (multi-action 11 stmia-sw-action)=0A= + (multi-action 12 stmia-sw-action)=0A= + (multi-action 13 stmia-sw-action)=0A= + (multi-action 14 stmia-sw-action)=0A= + (multi-action 15 stmia-action-r15)=0A= + (set rn addr))=0A= + )=0A= +=20=0A= (define-pmacro (stmda-action-r15 ignore)=0A= (sequence ()=0A= (set (mem WI addr) (add (reg WI h-gr 15) 4))=0A= (set addr (sub addr 4)))=0A= )=0A= =20=20=0A= + (define-pmacro (stmda-sw-action bit-num)=0A= + (sequence ()=0A= + (if (and reglist (sll 1 15))=0A= + (set (mem WI addr) (reg WI h-gr bit-num))=0A= + (set (mem WI addr) (reg WI h-gr-usr (sub bit-num 8))))=0A= + (set addr (sub addr 4)))=0A= + )=0A= +=20=0A= (define-pmacro (stmda-action bit-num)=0A= (sequence ()=0A= (set (mem WI addr) (reg WI h-gr bit-num))=0A= ***************=0A= *** 1920,1925 ****=0A= --- 2370,2400 ----=0A= (multi-action 0 stmda-action))=0A= )=0A= =20=20=0A= + (dnai stmda-sw "Store multiple registers (postindex, decrement, switch)"= =0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1)=0A= + (f-write-back? 0) (f-load? 0) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 15 stmda-action-r15)=0A= + (multi-action 14 stmda-sw-action)=0A= + (multi-action 13 stmda-sw-action)=0A= + (multi-action 12 stmda-sw-action)=0A= + (multi-action 11 stmda-sw-action)=0A= + (multi-action 10 stmda-sw-action)=0A= + (multi-action 9 stmda-sw-action)=0A= + (multi-action 8 stmda-sw-action)=0A= + (multi-action 7 stmda-action)=0A= + (multi-action 6 stmda-action)=0A= + (multi-action 5 stmda-action)=0A= + (multi-action 4 stmda-action)=0A= + (multi-action 3 stmda-action)=0A= + (multi-action 2 stmda-action)=0A= + (multi-action 1 stmda-action)=0A= + (multi-action 0 stmda-action))=0A= + )=0A= +=20=0A= (dnai stmda-wb "Store multiple registers (postindex, decrement, writeback= )"=0A= ()=0A= "FIXME"=0A= ***************=0A= *** 1946,1951 ****=0A= --- 2421,2451 ----=0A= (set rn addr))=0A= )=0A= =20=20=0A= + (dnai stmda-sw-wb "Store multiple registers (postindex, decrement, switch= , writeback)"=0A= + ()=0A= + "FIXME"=0A= + (+ cond (f-op3 4) (f-preindex? 0) (f-up-down 0) (f-load-psr? 1)=0A= + (f-write-back? 1) (f-load? 0) rn reglist)=0A= + (sequence ((WI addr))=0A= + (set addr rn)=0A= + (multi-action 15 stmda-action-r15)=0A= + (multi-action 14 stmda-sw-action)=0A= + (multi-action 13 stmda-sw-action)=0A= + (multi-action 12 stmda-sw-action)=0A= + (multi-action 11 stmda-sw-action)=0A= + (multi-action 10 stmda-sw-action)=0A= + (multi-action 9 stmda-sw-action)=0A= + (multi-action 8 stmda-sw-action)=0A= + (multi-action 7 stmda-action)=0A= + (multi-action 6 stmda-action)=0A= + (multi-action 5 stmda-action)=0A= + (multi-action 4 stmda-action)=0A= + (multi-action 3 stmda-action)=0A= + (multi-action 2 stmda-action)=0A= + (multi-action 1 stmda-action)=0A= + (multi-action 0 stmda-action)=0A= + (set rn addr))=0A= + )=0A= =0C=0A= ; Coprocessor instructions.=0A= ; Currently not implemented, so omit these, such that we take the=0A= ------=_NextPart_000_0003_01C25345.7E2FB5E0--