From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3043 invoked by alias); 4 Nov 2002 12:23:01 -0000 Mailing-List: contact cgen-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sources.redhat.com Received: (qmail 3004 invoked from network); 4 Nov 2002 12:22:59 -0000 Received: from unknown (HELO kiruna.synopsys.com) (204.176.20.18) by sources.redhat.com with SMTP; 4 Nov 2002 12:22:59 -0000 Received: from mother.synopsys.com (mother.synopsys.com [146.225.100.171]) by kiruna.synopsys.com (Postfix) with ESMTP id 48D2BF946 for ; Mon, 4 Nov 2002 04:19:33 -0800 (PST) Received: from fr02.synopsys.com (localhost [127.0.0.1]) by mother.synopsys.com (8.9.1/8.9.1) with ESMTP id EAA07062 for ; Mon, 4 Nov 2002 04:18:39 -0800 (PST) Received: from michaelclap (localhost [127.0.0.1]) by fr02.synopsys.com (8.9.1/8.9.1) with SMTP id NAA27221 for ; Mon, 4 Nov 2002 13:19:28 +0100 (MET) From: "Michael Chapman" To: Subject: Disassembly of instruction with 4 bit opcode Date: Mon, 04 Nov 2002 04:23:00 -0000 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8bit X-Priority: 3 (Normal) X-MSMail-Priority: Normal Importance: Normal X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 X-SW-Source: 2002-q4/txt/msg00021.txt.bz2 I have now got the assembler working. However I still have a little problem with disassembly which I do not understand. The problem is with the "call" instructions which use only 4 bits of the opcode using the remained for the address. Everything is strictly little endian with the opcode always appearing in the least significant 8 bits (or 4 bits in the case of call) of the instruction. When I dissassemble the following (listing output from the assembler) Dw32 GAS test1.asm page 1 1 2 0000 06100010 start: mov r1, #0x1000 3 4 0004 06302800 mov r3, #low(msg) 5 0008 56230000 l1: ldsb r2, (r3)0x0 6 000c 4120 cmp r2, #0 7 000e 8A0B beq finish 8 0010 CC000000 call putc 9 0014 2131 add r3, #1 10 0016 FAF8 bra l1 11 12 0018 A62000F0 putc: st r2, (r0)0xf000 13 001c 0620FFFF mov r2, #0xffff I get $ od -d test1.o test1.o: file format elf32-dw32 Disassembly of section .text: 00000000 : 0: 06 10 00 10 mov r1,#0x1000 4: 06 30 30 00 mov r3,#0x30 00000008 : 8: 56 23 00 00 ldsb r2,(r3)0x0 c: 41 20 cmp r2,#0x0 e: 8a 0f beq.s 2e 10: cc 00 *unknown* 12: 00 00 mov r0,r0 14: 21 31 add r3,#0x1 16: fa f8 bra.s 8 00000018 : 18: a6 20 00 f0 st r2,(r0)0xf000 1c: 06 20 ff ff mov r2,#0xffff The relevant bits of my cgen .cpu file are (define-arch (name dw32) (comment "DW32") (insn-lsb0? #t) (machs dw32) (isas dw32) ) ; Attributes ; Instruction set parameters. (define-isa ; Name of the ISA. (name dw32) (comment "Basic DW32 instruction set") ; (Size of unknown instructions) (default-insn-word-bitsize 16) ; Shortest instruction is 16 bits (default-insn-bitsize 32) (base-insn-bitsize 32) ) ; CPU family definitions. (define-cpu ; CPU names must be distinct from the architecture name and machine names. ; The "b" suffix stands for "base" and is the convention. ; The "f" suffix stands for "family" and is the convention. (name dw32bf) (comment "DW32 generic cpu") (endian little) (word-bitsize 32) ) ; Opcode fields (dnf f-opcode "opcode" () 7 8) (dnf f-call-opcode "call opcode" () 3 4) ; absolute, 28-bit (shifted 1 bit to right) (df f-abs28 "abs28" (ABS-ADDR) 31 28 UINT ((value pc) (sra WI value (const 1))) ((value pc) (sll WI value (const 1)))) (dni call-abs28 "call abs28" (UNCOND-CTI) "call $abs28" (+ (f-call-opcode #xc) abs28) (set pc abs28) () ) Any ideas as to what my problem is? Thanks for any help, Mike Chapman