Multiple ISAs for opcodes

Multiple ISAs for opcodes

[Ben Elliston]

Hi,

I'm trying to generate the opcodes files for a port which has two
ISAs.  The ISA shares some instruction names and this leads to
collisions in the cgen_insn_type enum (in the <arch>-opc.h file).

Before I work towards a solution to this, I'm trying to understand the
workings of the cgen-generated opcodes files.  Was it the intention
that a single set of files should be able to handle the entire
architecture?  If so, would the right fix be to include the ISA name
in the generated symbols to prevent these name collisions?

Ben

Multiple ISAs for opcodes

[Doug Evans]

Ben Elliston writes:
 > I'm trying to generate the opcodes files for a port which has two
 > ISAs.  The ISA shares some instruction names and this leads to
 > collisions in the cgen_insn_type enum (in the <arch>-opc.h file).

For the sake of discussion, is this something akin to arm vs thumb?

 > Before I work towards a solution to this, I'm trying to understand the
 > workings of the cgen-generated opcodes files.  Was it the intention
 > that a single set of files should be able to handle the entire
 > architecture?  If so, would the right fix be to include the ISA name
 > in the generated symbols to prevent these name collisions?

Re: Multiple ISAs for opcodes

[Ben Elliston]

Hi Doug,

   For the sake of discussion, is this something akin to arm vs thumb?

Yes, well and truly similar enough.

Ben

Re: Multiple ISAs for opcodes

[Ben Elliston]

   For the sake of discussion, is this something akin to arm vs thumb?

Yes.  Here's my analysis of the situtation:

	* fields, operands, instructions are deliniated by the isa
	  in my port (just like arm,thumb).

	* a pair of the opcodes files need to be completely generated down
	  this axis, modulo things in common -- but what are they?

What's a good way to proceed?

Ben

Multiple ISAs for opcodes

[Ben Elliston]

Hi,

I posted a question to the list some weeks ago and received no responses of
substance -- that surprises me.  Rather than type my message again, here is
a link to the archived original:

	http://sources.redhat.com/ml/cgen/2000-q4/msg00031.html

So -- any thoughts?

Thanks, Ben

Multiple ISAs for opcodes

[Doug Evans]

Ben Elliston writes:
 > Hi,
 > 
 > I posted a question to the list some weeks ago and received no responses of
 > substance -- that surprises me.  Rather than type my message again, here is
 > a link to the archived original:
 > 
 > 	http://sources.redhat.com/ml/cgen/2000-q4/msg00031.html
 > 
 > So -- any thoughts?

This is new ground (albeit barely).  What seems reasonable?

You could either have one enum that contains everything,
or you could generate two opc.h's, one for each ISA.
In and of itself, I prefer the latter.

Re: Multiple ISAs for opcodes

[Ben Elliston]

   This is new ground (albeit barely).  What seems reasonable?

   You could either have one enum that contains everything, or you could
   generate two opc.h's, one for each ISA. In and of itself, I prefer the
   latter.

Agreed.  Is there any work required to make this work, other than configury
hacks?  Thanks,

Ben

Re: Multiple ISAs for opcodes

[Frank Ch. Eigler]

Hi -

: [...] So -- any thoughts [re. multiple ISAs in opcodes/]?

For an internal port, several ISAs are plopped together in one set
of opcodes files, separated by ISA.  Instruction names (not mnemonics),
ifields, etc., are all suffixed to avoid collisions.  Sim-side code is
generated into mostly independent files (separate @prefix@).

It works fine.  Look around the code base for a certain co-processor.

- FChE
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