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To: "Michael Chapman" <Michael.Chapman@synopsys.com>
Cc: <cgen@sources.redhat.com>
Subject: Re: Disassembly of instruction with 4 bit opcode
References: <NEBBIAJILEHBJOLKLAGOAECICJAA.michaelc@synopsys.com>
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From: Ben Elliston <bje@redhat.com>
Date: Mon, 04 Nov 2002 04:42:00 -0000
In-Reply-To: "Michael Chapman"'s message of "Mon, 4 Nov 2002 13:19:28 +0100"
Message-ID: <m3znsp5xbo.fsf@scooby.brisbane.redhat.com>
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Hi Michael,

>>>>> "Michael" == Michael Chapman <Michael.Chapman@synopsys.com> writes:

  Michael> The problem is with the "call" instructions which use only
  Michael> 4 bits of the opcode using the remained for the address.
  Michael> Everything is strictly little endian with the opcode always
  Michael> appearing in the least significant 8 bits (or 4 bits in the
  Michael> case of call) of the instruction.  When I dissassemble the
  Michael> following (listing output from the assembler)
  [...]
  Michael>   10:	cc 00       	*unknown*

Investigate using something like this in your <arch>.opc file:

  /* Override disassembly hashing - there are variable bits in the top
     byte of these instructions.  */
  #define CGEN_DIS_HASH_SIZE 8
  #define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)

Cheers, Ben