From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32332 invoked by alias); 10 Feb 2014 21:31:33 -0000 Mailing-List: contact cgen-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cgen-owner@sourceware.org Received: (qmail 32314 invoked by uid 89); 10 Feb 2014 21:31:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.1 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 10 Feb 2014 21:31:31 +0000 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s1ALVSA7014863 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 10 Feb 2014 16:31:29 -0500 Received: from fche.csb (vpn-235-28.phx2.redhat.com [10.3.235.28]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s1ALVSTV008793; Mon, 10 Feb 2014 16:31:28 -0500 Received: by fche.csb (Postfix, from userid 2569) id C05AD5823F; Mon, 10 Feb 2014 16:31:27 -0500 (EST) To: Usha Gupta Cc: cgen Subject: Re: Help needed for porting opcodes for CISC architecture References: From: fche@redhat.com (Frank Ch. Eigler) Date: Mon, 10 Feb 2014 21:31:00 -0000 In-Reply-To: (Usha Gupta's message of "Mon, 3 Feb 2014 23:04:52 +0530") Message-ID: User-Agent: Gnus/5.1008 (Gnus v5.10.8) Emacs/21.4 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-IsSubscribed: yes X-SW-Source: 2014-q1/txt/msg00004.txt.bz2 Usha Gupta writes: > [...] > (default-insn-bitsize 8) > (base-insn-bitsize 16) > (default-insn-word-bitsize 16 ) > (word-bitsize 16 ) OK (though you might need to raise base-insn-bitsize). > [...] > Here are some of the instruction formats : > > 1-byte instruction: > 1) IIIIIrrr - 5 bits opcode , 3 bits for register operand (one of > the operand is fixed register, implied from the opcode) > 2) IIIddddd - 3 bits opcode, 5 bit displacement > > 2-byte instruction: > 1) IIIIIsss IIIIIttt - 5-bit opcode, 3-bit register operand > (source), 5-bit opcode, 3-bit register operand (destination) > > How do I define instructions of varying length? Presumably those IIIII's don't overlap - i.e., the hardware can tell from the first byte that it's a 2-byte instruction (and more opcode bits need to be fetched). In cgen, instruction opcodes need not be single fields nor contiguous; just specify one ifield per unique opcode piece. - FChE