From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from omta002.cacentral1.a.cloudfilter.net (omta002.cacentral1.a.cloudfilter.net [3.97.99.33]) by sourceware.org (Postfix) with ESMTPS id B3B003858D32 for ; Sun, 12 Mar 2023 17:16:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B3B003858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=Shaw.ca Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=shaw.ca Received: from shw-obgw-4002a.ext.cloudfilter.net ([10.228.9.250]) by cmsmtp with ESMTP id bNglpEEBojvm1bPIepYtZ3; Sun, 12 Mar 2023 17:16:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=shaw.ca; s=s20180605; t=1678641360; bh=EmJ2xD20Q5UGowA1PNPA1f+9AT/Ka1M6Ohd/HQ+00fw=; h=From:To:Reply-To:Date:Subject; b=k/tmWmYxGtMfqmiPt950iSX4rny2/dXwPxRoRNqWT1Cah+5YE1CBLcfvAjCOGDZtl c6VtqNs7N0L9c0AA8VJDdh8L6tk7h9c2NhI909AKTrwW1qyyh+NeKPR+NTTisU8CXc iLVMRYGbHOcSSfAAloXTu6t+T6nI504iqoFLmyv3kVVwh2714mWWakjKWSfCUd+DGP sirq6tpuOGtFIHeKSAhxeGv85SrisVy6WAqm0Mv0fKBuawCWlzyUMBmakHR0s5GRHP aHw6IlzgIrDRK2FoP0CcVjj0qRpDYUnCkrp8eOquzT8+dve3C4n5BdE8qWnUz4LzC7 4EumQkJwBEpCw== Received: from localhost.localdomain ([184.64.102.149]) by cmsmtp with ESMTP id bPIepV4uPyAOebPIepV7GO; Sun, 12 Mar 2023 17:16:00 +0000 X-Authority-Analysis: v=2.4 cv=e5oV9Il/ c=1 sm=1 tr=0 ts=640e08d0 a=DxHlV3/gbUaP7LOF0QAmaA==:117 a=DxHlV3/gbUaP7LOF0QAmaA==:17 a=5_s1rtZIAAAA:8 a=DZ2AbChif5qwIYwhOuwA:9 a=7-3sKM-zqIYA:10 a=3dMv4P1n_z9a81GE33Fp:22 From: "Cygwin cpuid Maintainer" To: "Cygwin Announcements" Reply-To: "Cygwin" Date: Sun, 12 Mar 2023 11:15:02 -0600 Message-Id: <20230312111502.60214-1-Brian.Inglis@Shaw.ca> Subject: Updated: cpuid 20230306 X-CMAE-Envelope: MS4xfAl/q+eMF8sTCFKXqCO0/WSkvv6w6r/fA+VAAYU1iaOMCkeRLFN7q+oSrYz+7CjPgBbx0HpZbhp4ZbZRN9/qoiKSMvsxpeu6e5f4Zyi8jKOfXSgt8EG3 fbwyO2lJ5N29dLV7+105wHA2ktffPuCzKGkE3QDdgz/2w2ysMkYHZK+dTZM/zPYeK2ovjTs150+uTTYOddKZVLl9XixkF97PDVU= X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_NUMSUBJECT,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The following package has been upgraded in the Cygwin distribution: * cpuid 20230306 Displays detailed information about the CPU(s) gathered from the CPUID instruction, and also determines the exact model of CPU(s). Whereas /proc/cpuinfo is like an abstract of the features important to Linux in a system, cpuid is a standalone utility which writes a paper expounding on every feature in each CPU's architecture and what it can do, at about the one line per bit level. It is updated and released frequently to stay current with Intel and AMD information and supports other vendors' chips. See the project home page for more information: http://etallen.com/cpuid.html For information about changes since the previous Cygwin release, see below or /usr/share/doc/cpuid/ChangeLog after installation. Tue Mar 6 2023 20230306 * Based on Intel-Linux-Processor-Microcode-Data-Files (ILPMDF*), made the following (synth) changes: cpuid.c: - Updated (0,6),(3,7),8 Bay Trail with stepping name C0. - Added (0,6),(4,5),1 Haswell-ULT C0/D0 stepping. - Corrected (0,6),(4,6),1 Crystal Well to C0 stepping. - Updated (0,6),(4,7),1 Broadwell to include E0 stepping. - Added (0,6),(5,5),3 Skylake B1 (Xeon Scalable). - Added (0,6),(5,5),5 Skylake A0 (Xeon Scalable). - Added (0,6),(5,5),11 Cooper Lake A1 (Xeon Scalable). - Updated (0,6),(5,14),3 Skylake-H/S/E3, adding N0 & S0 steppings. - Added (0,6),(6,10),5 Ice Lake C0 (Xeon Scalable). - Added (0,6),(6,12),1 Ice Lake B0. - Updated (0,6),(8,6),4 Snow Ridge with stepping B0. - Updated (0,6),(8,6),5 Snow Ridge with stepping B1. - Added (0,6),(8,6),1 Lakefield B2/B3 stepping. - Corrected (0,6),(8,12),1 Tiger Lake stepping to B1. - Added (0,6),(8,12),2 Tiger Lake C0. - Added (0,6),(8,14),10 Coffee Lake D0. - Added (0,6),(8,14),13 Whiskey Lake-U V0 stepping. - Added (0,6),(8,15) Sapphire Rapids numerous steppings. - Updated (0,6),(9,12) Jasper Lake with stepping A1. - Differentiate (0,6),(8,10) Lakefield P-cores from Tremont E-cores, much as previously for Alder Lake & Raptor Lake. - In decode_uarch_intel, for known Hybrid chips (Alder Lake, Raptor Lake & Lakefield), only decode the uarch if it's one of the two known hybrid types. However, some (0,6),(9,7) Alder Lake's are non-hybrid (Golden Cove only), so also decode core type == 0x00 there. - In the Intel Core era, uarch families are identified only by the initial uarch in the family. So the family names in {braces}, which also are uarch names, can be confusing. So, change (synth) and (uarch synth) for those families to explain the relationships between the subsequent uarch and the initial uarch, in the form of "shrink of", "optim of", and the unusual "backport of". - Added (4th Gen) to the (synth) description of (10,15),(1,*) AMD EPYC Genoa. - Updated (synth) for (10,15),(7,*) AMD Phoenix & Phoenix 2 CPUs to claim 4nm process.