From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by sourceware.org (Postfix) with ESMTPS id 0EC923858D28 for ; Sun, 31 Mar 2024 02:40:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0EC923858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=SystematicSW.ab.ca Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=SystematicSW.ab.ca ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0EC923858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=216.40.44.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1711852807; cv=none; b=QGjGm2JGRc5SxdvZWaVoawzXcJ4adfr217mgq9qcEmUVFyEqarLZqnijuqKb25B9ZbzsTeIBnRNqGh4vJD9xauwz/BjDUrWUBqjNR5f/7+j2T+EyrZrhcfSj6azOmlM6wERrus1gZvJ1FzTcwa6pTvGxfPXGsKvKv+4jM4Rqg98= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1711852807; c=relaxed/simple; bh=FH8euy5aHHS3ptk1q1+/bNqUUrMH9OlXcZPCIAt1gvc=; h=From:To:Date:Message-Id:Subject; b=FuuoVyM48r8SIM9+r7cu8lPRkvZEmLpeawh2rIL2HK/RvKzeb7F7p2KpopqrMwLLgSABnaM4FNjhiFhWMDMOMBppAr0LogwgtdNRy4Qj4LkF+qdCfrvrYu9U6OBssBoiC2csHFpuesn3GPrjqrOsCjZYW1PZR/rl7S/m0UCY0m0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from omf11.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay06.hostedemail.com (Postfix) with ESMTP id 7AC03A0C8D for ; Sun, 31 Mar 2024 02:40:05 +0000 (UTC) Received: from [HIDDEN] (Authenticated sender: Brian.Inglis@SystematicSW.ab.ca) by omf11.hostedemail.com (Postfix) with ESMTPA id 4FD342002C for ; Sun, 31 Mar 2024 02:40:04 +0000 (UTC) From: "Cygwin cpuid Maintainer" To: "Cygwin Announcements" Reply-To: "Cygwin" Date: Sat, 30 Mar 2024 20:38:53 -0600 Message-Id: <20240330203853.62175-1-Brian.Inglis@SystematicSW.ab.ca> Subject: Updated: cpuid 20240324 X-Rspamd-Server: rspamout06 X-Rspamd-Queue-Id: 4FD342002C X-Stat-Signature: 845bx7goac43fmhwes94eu44e78f71x7 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Session-Marker: 427269616E2E496E676C69734053797374656D6174696353572E61622E6361 X-Session-ID: U2FsdGVkX18TzSEy6XsGRQO3otyi61EzPr8ejxEDSuQ= X-HE-Tag: 1711852804-867785 X-HE-Meta: U2FsdGVkX1+E1l5n2NFJUSHaKhkexk3Yi/zGq+exDpzABhyOJp8dIka6U2TViB7tFpZo1ySYskuiV+4W876k16NufDzzugKVodc2E+0qSX85Zhd/ljmJ4fO5aYx9+DlIRbczFOS7a/KWeslEi21t8O8lFIw0SJUpCORXUWGlAHeAwSQuY6dQ7/PAJ8WrQegbpHCD18DjnHJJye/nU9c7pWYU+EpXI5WWgEeYkVGAqPzzx1E+Zn5gp7f/sYPVUwfGwTeRzzd9f9shO/oe784mOjHwQWRQ4yV7kXOSUDglXj2VvL0LYb+YYmEbTPpu3vtih/304X1IckV/hZXIicTgM7nP3yCb/yNLZjHLElMyjV1tVMEW/KUtL7UbG4AdiSK3UicNM9++066U2kbnH8R6F6SjZh1+/z9K X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The following package has been upgraded in the Cygwin distribution: * cpuid 20240324 Displays detailed information about the CPU(s) gathered from the CPUID instruction, and also determines the exact model of CPU(s). Where /proc/cpuinfo shows features important to a system, cpuid shows what every feature in each CPU's architecture does. It is updated and released frequently to stay current with Intel and AMD information and supports other vendors' chips. See the project home page for more information: http://etallen.com/cpuid.html For information about changes since the previous Cygwin release, see below or /usr/share/doc/cpuid/ChangeLog after installation. 2024 Mar 24 Sun 20240324 cpuid.man: Added new Intel docs. cpuid.c: - Updated synth decoding for (0,6),(12,15),2 Emerald Rapids A1/R1. - In do_real(), for the 0x1b leaf, add a sanity check to avoid infinite recursion if a hypervisor never reports invalid (0) on any subleaf. The sanity check checks for a subleaf identical to its predecessor, which is not reasonable. - Added synth & uarch decoding for (0,6),(13,13) Clearwater Forest. - Updated (0,6),(8,12),1 to include stepping B0, from ILPMDF* - Updated (0,6),(11,15),5 to Raptor Lake stepping H0, based on preponderance of evidence. - Added synth decoding for (0,6),(10,10) Core Ultra CPUs. - Updated (0,6),(11,7) to include Core i*-14000. Some CPUs have this branding, and it's not clear what's different from the Core i*-13000 versions. The steppings don't seem to matter. Inspection suggests maybe CET_SSS. - Corrected synth decoding for (10,15),(1,8) Storm Peak: Ryzen Threadripper 7000. - Added synth decoding for (10,15),(7,5),2 AMD Ryzen Phoenix F2. - Added very preliminary uarch decoding for (10,15),(6,0) and (10,15),(7,0), both Zen 5. - Changed preliminary synth decoding for (0,6),(11,5) to Arrow Lake, based on Intel SDE 9.33.0. - Added synth decoding for (0,6),(8,13),0 Tiger Lake-H P0 stepping. - Added synth decoding for (0,6),(11,13),0 Lunar Lake A0 stepping. - Changed uarch decoding for (0,6),(13,13) to Darkmont, the presumed uarch for Clearwater Forest. - Added 12/1/eax AEX attribute enabled, as described by Scott Raynor, Intel. - Added 7/1/eax NMI-source reporting. - Added 7/1/eax INVD prevention after BIOS done. - Renamed 7/1/ebx PKNDKB instruction. - Added 7/1/edx URDMSR, UWRMSR instructions. - Added 0xa/ebx additional events. - Added 0xf/1/eax non-CPU agent features. - For 0xf/0/edx supports L3 cache monitoring, removed redundant "QoS". - Renamed print_10_n_{eax,ecx} -> print_10_12_{eax,ecx}. - Added 0x10/0/ebx cache bandwidth allocation supported. - Replaced 0x10/{1,2}/ecx: non-CPU agent support. - Renamed 0x10/{1,2}/ecx: non-contiguous bitmask supported. - Added 0x10/5 Cache Bandwidth Allocation decoding. - Renamed 0x23/0/ebx IA32_PERFEVTSELx EQ bit supported. - Added 0x23/2 ACR counters bitmaps. - Corrected synth decoding for (10,15),(10,x) to EPYC (4th Gen) (server CPUs), instead of Ryzen (desktop CPUs). - Added (0,6),(12,12) Panther Lake synth decoding from LX*, but left out corresponding uarch decoding which is alls rumors currently: maybe Panther Cove, Cougar Cove, or something else. - Added hypervisor+0xc ebx isolation type new value: TDX (3) from LX*. - Added (11,5),(0,0) Zen 5 uarch from LX*. - To decode_uarch_intel, added (0,6),(11,12) & (0,6),(11,13) Lion Cove & Skymont as uarch underpinning Lunar Lake. - Added 0x80000021/eax selective branch prediction barrier, PRED_CMD[IBPB] flushes branch type preds. They appear to be only synthetic flags provided for hypervisor guests! - Added 0x80000021/eax CPU not affected by SRSO flag, from LX*. - Added (10,15),(8&9,0) uarch & synth decoding for AMD Instinct MI300, from LKML: https://lkml.org/lkml/2023/7/20/668 patches. In the past, Instinct MI* described just the GPU, but they seem to be conflating them into a product name here. - Added prelim uarch decoding for (11,15),(2,0) & (11,15),(4,0), both Zen 5, based on engr samples. No synth decoding yet, because it isn't known yet. - Added prelim synth decoding for (0,6),(11,12) Lunar Lake from Intel SDE 9.24.0 misc/cpuid/lnl/cpuid.def. No uarch decoding, because Lunar Lake uarch name is not known yet. - Added prelim synth decoding for (0,6),(9,5) Sapphire Rapids from Intel SDE 9.24.0 misc/cpuid/spr/cpuid.def. - Added synth decoding for (0,6),(11,7),0 Raptor Lake A0 stepping, from Coreboot*. - Added 7/1/eax SHA512, SM3 & SM4 instructions. - Added 7/1/ebx TSE PBNDKB instruction. - Added 7/1/ebx AVX-VNNI-INT16 instructions. - Added 7/1/edx UIRET flexibly updates UIF. - Added 0x1b/2 TSE target. - Corrected sub-leaf walk of leaf 0x1b to stop immediately if sub-leaf 0 is invalid. - Added (uarch synth) & (synth) decoding for (0,6),(12,5) Arrow Lake based on Lion Cove & Skymont. - Added 0x80000008/ebx IBPB_RET. - Renamed 0x8000000a/edx extended LVT AVIC access changes. - Renamed 0x8000000a/edx guest VMCB addr check. - Added 0x8000000a/edx bus lock threshold. - Renamed several 0x80000020 leaves & fields. - Added 0x80000020/0/ebx assignable bandwidth monitoring counters. - Added 0x80000020/0/ebx SDCI allocation enforcement - Added 0x80000020/5 PQoS Assignable Bandwidth Monitoring Counters. - Added (synth) decoding for (0,6),(10,10),4 Meteor Lake-M C0 stepping from Coreboot*.