From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 109180 invoked by alias); 7 Oct 2019 19:55:10 -0000 Mailing-List: contact cygwin-cvs-help@cygwin.com; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: cygwin-cvs-owner@cygwin.com Received: (qmail 109139 invoked by uid 9996); 7 Oct 2019 19:55:10 -0000 Date: Mon, 07 Oct 2019 19:55:00 -0000 Message-ID: <20191007195510.109137.qmail@sourceware.org> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Ken Brown To: cygwin-cvs@sourceware.org Subject: [newlib-cygwin] fhandler_proc.cc(format_proc_cpuinfo): fix cache size X-Act-Checkin: newlib-cygwin X-Git-Author: Brian Inglis X-Git-Refname: refs/heads/master X-Git-Oldrev: e06f2fbde7d9d8ca3d363035dacbbc4b81e29c9a X-Git-Newrev: acc8849f844f2dbc41ef8da9687bbe1c1d5b3bdc X-SW-Source: 2019-q4/txt/msg00001.txt.bz2 https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;h=acc8849f844f2dbc41ef8da9687bbe1c1d5b3bdc commit acc8849f844f2dbc41ef8da9687bbe1c1d5b3bdc Author: Brian Inglis Date: Mon Oct 7 10:22:58 2019 -0600 fhandler_proc.cc(format_proc_cpuinfo): fix cache size Fix cache size return code handling and make AMD/Intel code common. Diff: --- winsup/cygwin/fhandler_proc.cc | 45 +++++++++++++++++------------------------- 1 file changed, 18 insertions(+), 27 deletions(-) diff --git a/winsup/cygwin/fhandler_proc.cc b/winsup/cygwin/fhandler_proc.cc index 48476be..13cc368 100644 --- a/winsup/cygwin/fhandler_proc.cc +++ b/winsup/cygwin/fhandler_proc.cc @@ -744,6 +744,8 @@ format_proc_cpuinfo (void *, char *&destbuf) int cache_size = -1, clflush = 64, cache_alignment = 64; + long (*get_cpu_cache) (int, uint32_t) = NULL; + uint32_t max; if (features1 & (1 << 19)) /* CLFSH */ clflush = ((extra_info >> 8) & 0xff) << 3; if (is_intel && family == 15) @@ -751,45 +753,34 @@ format_proc_cpuinfo (void *, char *&destbuf) if (is_intel) { extern long get_cpu_cache_intel (int sysc, uint32_t maxf); - long cs; - - cs = get_cpu_cache_intel (_SC_LEVEL3_CACHE_SIZE, maxf); - if (cs == -1) - cs = get_cpu_cache_intel (_SC_LEVEL2_CACHE_SIZE, maxf); - if (cs == -1) - { - cs = get_cpu_cache_intel (_SC_LEVEL1_ICACHE_SIZE, maxf); - if (cs != -1) - cache_size = cs; - cs = get_cpu_cache_intel (_SC_LEVEL1_DCACHE_SIZE, maxf); - if (cs != -1) - cache_size += cs; - } - else - cache_size = cs; - if (cache_size != -1) - cache_size >>= 10; + get_cpu_cache = get_cpu_cache_intel; + max = maxf; /* Intel uses normal cpuid levels */ } else if (is_amd) { extern long get_cpu_cache_amd (int sysc, uint32_t maxe); + get_cpu_cache = get_cpu_cache_amd; + max = maxe; /* AMD uses extended cpuid levels */ + } + if (get_cpu_cache) + { long cs; - cs = get_cpu_cache_amd (_SC_LEVEL3_CACHE_SIZE, maxe); - if (cs == -1) - cs = get_cpu_cache_amd (_SC_LEVEL2_CACHE_SIZE, maxe); - if (cs == -1) + cs = get_cpu_cache (_SC_LEVEL3_CACHE_SIZE, max); + if (cs <= 0) + cs = get_cpu_cache (_SC_LEVEL2_CACHE_SIZE, max); + if (cs <= 0) { - cs = get_cpu_cache_amd (_SC_LEVEL1_ICACHE_SIZE, maxe); - if (cs != -1) + cs = get_cpu_cache (_SC_LEVEL1_ICACHE_SIZE, max); + if (cs > 0) cache_size = cs; - cs = get_cpu_cache_amd (_SC_LEVEL1_DCACHE_SIZE, maxe); - if (cs != -1) + cs = get_cpu_cache (_SC_LEVEL1_DCACHE_SIZE, max); + if (cs > 0) cache_size += cs; } else cache_size = cs; - if (cache_size != -1) + if (cache_size > 0) cache_size >>= 10; } bufptr += __small_sprintf (bufptr, "cpu family\t: %d\n"