From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 80212 invoked by alias); 13 Apr 2018 03:01:49 -0000 Mailing-List: contact cygwin-help@cygwin.com; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: cygwin-owner@cygwin.com Mail-Followup-To: cygwin@cygwin.com Received: (qmail 80202 invoked by uid 89); 13 Apr 2018 03:01:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=no version=3.3.2 spammy=thermal, Supervisor, supervisor, mhz X-HELO: mail-ot0-f193.google.com Received: from mail-ot0-f193.google.com (HELO mail-ot0-f193.google.com) (74.125.82.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 13 Apr 2018 03:01:46 +0000 Received: by mail-ot0-f193.google.com with SMTP id m22-v6so8346269otf.8 for ; Thu, 12 Apr 2018 20:01:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:reply-to:from:date:message-id :subject:to; bh=L8n/0lUN2AIQvfzZ5oo9McVTejgn8rkPSo1UTcDhGKM=; b=RyrJKAoRRtf4KlOfb0XtbRYjsnQA0JNYHMhA3aEplWwsP2677ETwC9uGHmJAaVNTqF ENdRmSIWFWKt5aEudWxcZN52f+U5I+rIcQuxlxBYfHT6Y25cIPYlmTz2CHLiy2FBrmgo NS+mVhjVcXK0JIlLWqqB3k0HqpjOiKgLw6DfzjKflceC5kJStY5R21TJXS62R3Mnp+hw FB8HW2dnQphMPzgNJ0CspSSgmHBN+ZXssJ/nESLrjyNBO/nI9J9dirL8coRxVO4h6hlW xJ5fgCt7n/2cb2Gte8NyAhjlb7I6AlsD60gIj3nU1SkMVY8g9s1srvqbXalYOeGzvEz3 MbxA== X-Gm-Message-State: ALQs6tBdNA1tQjAnRQFGgL02toU01eWMfgCq9XMMZv/ZcuuVOXd2gvE7 zYHKXmlVN+OpTW4attJnuf+YwhW0sH+yyGV+7HETbSWP X-Google-Smtp-Source: AIpwx4+R/0XyVyqsZHTZdqiD3Gjr19qxtYECNKxOx5RlswJyrpomo9rdtweuntLncpzEP2HPnk/BvdAjsYazJHiWhVU= X-Received: by 2002:a9d:4389:: with SMTP id t9-v6mr2490067ote.262.1523588503712; Thu, 12 Apr 2018 20:01:43 -0700 (PDT) MIME-Version: 1.0 Received: by 10.74.62.206 with HTTP; Thu, 12 Apr 2018 20:01:43 -0700 (PDT) Reply-To: noloader@gmail.com From: Jeffrey Walton Date: Fri, 13 Apr 2018 03:01:00 -0000 Message-ID: Subject: Incorrect /proc/cpuinfo for AMD A6-9220 To: cygwin@cygwin.com Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2018-04/txt/msg00141.txt.bz2 Hi Everyone, I'm working on an AMD A6-9220 and seeing unusual results from /proc/cpuinfo. I think this may be an issue with the latest Cygwin. It may be present in earlier versions, too. Russinovich's coreinfo is shown below (https://docs.microsoft.com/en-us/sysinternals/downloads/coreinfo). Notice /proc/cpuinfo is missing aesni, pclmul, rdrand, SSE4.1, SSE4.2, AVX, etc. Jeff ***** Coreinfo ***** C:\Users\Test>coreinfo Coreinfo v3.31 - Dump information on system CPU and memory topology Copyright (C) 2008-2014 Mark Russinovich Sysinternals - www.sysinternals.com AMD A6-9220e RADEON R4, 5 COMPUTE CORES 2C+3G AMD64 Family 21 Model 112 Stepping 0, AuthenticAMD Microcode signature: 06006704 HTT * Multicore HYPERVISOR - Hypervisor is present VMX - Supports Intel hardware-assisted virtualization SVM * Supports AMD hardware-assisted virtualization X64 * Supports 64-bit mode SMX - Supports Intel trusted execution SKINIT * Supports AMD SKINIT NX * Supports no-execute page protection SMEP * Supports Supervisor Mode Execution Prevention SMAP - Supports Supervisor Mode Access Prevention PAGE1GB * Supports 1 GB large pages PAE * Supports > 32-bit physical addresses PAT * Supports Page Attribute Table PSE * Supports 4 MB pages PSE36 * Supports > 32-bit address 4 MB pages PGE * Supports global bit in page tables SS - Supports bus snooping for cache operations VME * Supports Virtual-8086 mode RDWRFSGSBASE * Supports direct GS/FS base access FPU * Implements i387 floating point instructions MMX * Supports MMX instruction set MMXEXT * Implements AMD MMX extensions 3DNOW - Supports 3DNow! instructions 3DNOWEXT - Supports 3DNow! extension instructions SSE * Supports Streaming SIMD Extensions SSE2 * Supports Streaming SIMD Extensions 2 SSE3 * Supports Streaming SIMD Extensions 3 SSSE3 * Supports Supplemental SIMD Extensions 3 SSE4a * Supports Streaming SIMDR Extensions 4a SSE4.1 * Supports Streaming SIMD Extensions 4.1 SSE4.2 * Supports Streaming SIMD Extensions 4.2 AES * Supports AES extensions AVX * Supports AVX intruction extensions FMA * Supports FMA extensions using YMM state MSR * Implements RDMSR/WRMSR instructions MTRR * Supports Memory Type Range Registers XSAVE * Supports XSAVE/XRSTOR instructions OSXSAVE * Supports XSETBV/XGETBV instructions RDRAND * Supports RDRAND instruction RDSEED - Supports RDSEED instruction CMOV * Supports CMOVcc instruction CLFSH * Supports CLFLUSH instruction CX8 * Supports compare and exchange 8-byte instructions CX16 * Supports CMPXCHG16B instruction BMI1 * Supports bit manipulation extensions 1 BMI2 * Supports bit manipulation extensions 2 ADX - Supports ADCX/ADOX instructions DCA - Supports prefetch from memory-mapped device F16C * Supports half-precision instruction FXSR * Supports FXSAVE/FXSTOR instructions FFXSR * Supports optimized FXSAVE/FSRSTOR instruction MONITOR * Supports MONITOR and MWAIT instructions MOVBE * Supports MOVBE instruction ERMSB - Supports Enhanced REP MOVSB/STOSB PCLMULDQ * Supports PCLMULDQ instruction POPCNT * Supports POPCNT instruction LZCNT * Supports LZCNT instruction SEP * Supports fast system call instructions LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode HLE - Supports Hardware Lock Elision instructions RTM - Supports Restricted Transactional Memory instructions DE * Supports I/O breakpoints including CR4.DE DTES64 - Can write history of 64-bit branch addresses DS - Implements memory-resident debug buffer DS-CPL - Supports Debug Store feature with CPL PCID - Supports PCIDs and settable CR4.PCIDE INVPCID - Supports INVPCID instruction PDCM - Supports Performance Capabilities MSR RDTSCP * Supports RDTSCP instruction TSC * Supports RDTSC instruction TSC-DEADLINE - Local APIC supports one-shot deadline timer TSC-INVARIANT * TSC runs at constant rate xTPR - Supports disabling task priority messages EIST - Supports Enhanced Intel Speedstep ACPI - Implements MSR for power management TM - Implements thermal monitor circuitry TM2 - Implements Thermal Monitor 2 control APIC * Implements software-accessible local APIC x2APIC - Supports x2APIC CNXT-ID - L1 data cache mode adaptive or BIOS MCE * Supports Machine Check, INT18 and CR4.MCE MCA * Implements Machine Check Architecture PBE - Supports use of FERR#/PBE# pin PSN - Implements 96-bit processor serial number PREFETCHW * Supports PREFETCHW instruction Maximum implemented CPUID leaves: 0000000D (Basic), 8000001E (Extended). Logical to Physical Processor Map: *- Physical Processor 0 -* Physical Processor 1 ***** /proc/cpuinfo ***** $ cat /proc/cpuinfo processor : 0 vendor_id : AuthenticAMD cpu family : 21 model : 112 model name : AMD A6-9220e RADEON R4, 5 COMPUTE CORES 2C+3G stepping : 0 cpu MHz : 1597.000 cache size : 0 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 1 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm pni cx16 lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs sse5 skinit wdt lwp fma4 tce nodeid_msr tbm perfctr_core perfctr_nb clflush size : 64 cache_alignment : 64 address sizes : 48 bits physical, 48 bits virtual power management: ts ttp tm 100mhzsteps hwpstate cpb eff_freq_ro processor : 1 vendor_id : AuthenticAMD cpu family : 21 model : 112 model name : AMD A6-9220e RADEON R4, 5 COMPUTE CORES 2C+3G stepping : 0 cpu MHz : 1597.000 cache size : 0 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 1 apicid : 1 initial apicid : 1 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm pni cx16 lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs sse5 skinit wdt lwp fma4 tce nodeid_msr tbm perfctr_core perfctr_nb clflush size : 64 cache_alignment : 64 address sizes : 48 bits physical, 48 bits virtual power management: ts ttp tm 100mhzsteps hwpstate cpb eff_freq_ro -- Problem reports: http://cygwin.com/problems.html FAQ: http://cygwin.com/faq/ Documentation: http://cygwin.com/docs.html Unsubscribe info: http://cygwin.com/ml/#unsubscribe-simple