[Bug 1001300] problème de commutation des taches

[Bug 1001300] problème de commutation des taches

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Christophe Coutand <ecos@hotmail.co.uk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |ecos@hotmail.co.uk

--- Comment #1 from Christophe Coutand <ecos@hotmail.co.uk> 2011-08-01 11:07:29 BST ---
Can you tell if the application crashes? Is the simulator correctly handling
the interrupt that is used for the kernel RTC? if not, the threads will never
go behind the cyg_thread_delay() call.

Christophe

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--- Comment #2 from atef <benhajatef@yahoo.fr> 2011-08-02 14:37:56 BST ---
(In reply to comment #1)
> Can you tell if the application crashes? Is the simulator correctly handling
> the interrupt that is used for the kernel RTC? if not, the threads will never
> go behind the cyg_thread_delay() call.
> 
> Christophe

how we can test the simulator correctly handling the interrupt ??

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--- Comment #3 from Christophe Coutand <ecos@hotmail.co.uk> 2011-08-03 01:50:54 BST ---
I don't know enough about the MIPS architecture to give you pointers. What type
of debugging facility do you have with the simulator? Can you set breakpoints
for debugging? If you get interrupts, you should hit the
__default_interrupt_vsr function call. The RTC clock is default mapped as
following:

Look inside packages\hal\mips\arch\current\include\hal_intr.h:

// The vector used by the Real time clock. The default here is to use
// interrupt 5, which is connected to the counter/comparator registers
// in many MIPS variants.

#ifndef CYGNUM_HAL_INTERRUPT_RTC
#define CYGNUM_HAL_INTERRUPT_RTC            CYGNUM_HAL_INTERRUPT_5
#endif

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--- Comment #7 from atef <benhajatef@yahoo.fr> 2011-08-07 04:39:23 BST ---
Thank you again,
how can i implement the eCos RTC clock using the vci-xicu, it must change the
file hal_intr.h, or the patch soclib.

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--- Comment #8 from Christophe Coutand <ecos@hotmail.co.uk> 2011-08-07 05:16:32 BST ---
In the plf_intr.h of the soclib package, you can overwrite the clock definition
provided from the hal_intr.h.

You must select the correct interrupt for the RTC clock:

#define CYGNUM_HAL_INTERRUPT_RTC YOUR_SOCLIB_TIMER_IRQ_NUM

and define the 3 macos used by eCos to access the clock:

externC CYG_WORD32 cyg_hal_clock_period;
#define CYGHWR_HAL_CLOCK_PERIOD_DEFINED

#define HAL_CLOCK_INITIALIZE( _period_ )           \
CYG_MACRO_START                                           \
     /* Place code here * /
    cyg_hal_clock_period = _period_;                       \
CYG_MACRO_END

#define HAL_CLOCK_RESET( _vector_, _period_ )   \
     /* Place code here * /
CYG_MACRO_END

#define HAL_CLOCK_READ( _pvalue_ )                 \
CYG_MACRO_START                                           \
     /* Place code here * /
CYG_MACRO_END

#define CYGHWR_HAL_CLOCK_CONTROL_DEFINED

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--- Comment #9 from atef <benhajatef@yahoo.fr> 2011-08-08 03:38:15 BST ---
I fail to operate this platform, I am sending the file top.cc (which contains
the description of the MIPS architecture) and the file plf_intr.h. This error
message is displayed during simulation:
[GDB] CPU0 (cpu0) cycle: ................ PC: bfc0039c FAULT: bad address.
end I not find words to thank you for your help.





                            plf_intr.h




#ifdef CYGONCE_HAL_PLF_INTR_H
#define CYGONCE_HAL_PLF_INTR_H

#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>

#define HAL_PLATFORM_RESET()              CYG_EMPTY_STATEMENT
#define HAL_PALTFORM_RESET_ENTRY        0xbfc00000

#define CYGNUM_HAL_INTERRUPT_RTC  p_irq_in[0]


/*  code de trois macro*/




#define CYGHWR_HAL_CLOCK_CONTROL_DEFINE
#endif










                                      TOP.CC


#include <iostream>
#include <cstdlib>
#include <stdexcept>

#define CONFIG_GDB_SERVER

#include "mapping_table.h"

#if defined(CONFIG_GDB_SERVER)
# include "gdbserver.h"
#endif

#include "vci_xcache_wrapper.h"
#include "vci_ram.h"
#include "vci_heterogeneous_rom.h"
#include "vci_multi_tty.h"
//#include "vci_timer.h"
#include "vci_locks.h"
#include "vci_xicu.h"
#include "vci_vgmn.h"

// You may set the SOCLIB_GDB environment variable to
// START_FROZEN before starting the simulator.

#include "mips32_vmem.h"

typedef soclib::common::GdbServer<soclib::common::Mips32El4kpIss> Processor;

int _main(int argc, char *argv[])
{
    // Avoid repeating these everywhere
    using soclib::common::IntTab;
    using soclib::common::Segment;
    size_t cpu_count = 1;

    if (argc < 2)
      return 1;

    // Define our VCI parameters
    typedef soclib::caba::VciParams<4,9,32,1,1,1,8,1,1,1> vci_param;
    //   
soclib::common::GdbServer<soclib::common::Mips32El4kpIss>::start_forzen();
    // Mapping table
    soclib::common::MappingTable maptab(32, IntTab(8), IntTab(8), 0x00c00000);

    maptab.add(Segment("rom",   0x1fc00000, 0x00100000,  IntTab(0), false));
    maptab.add(Segment("ram" ,  0x80000000, 0x00400000 , IntTab(1), true));

    maptab.add(Segment("tty"  , 0xc0c00000,  0x10, IntTab(2), false));
    maptab.add(Segment("xicu",   0xd0c00200, 4096, IntTab(3), false));
    //  maptab.add(Segment("timer", 0xb0c00000,0x00000100, IntTab(2), false));

    // Signals

    sc_core::sc_clock signal_clk("signal_clk");
    sc_core::sc_signal<bool> signal_resetn("signal_resetn");

    sc_core::sc_signal<bool> signal_cpu_it[cpu_count][Processor::n_irq]; 

    soclib::caba::VciSignals<vci_param> signal_vci_m[cpu_count];

    soclib::caba::VciSignals<vci_param> signal_vci_xicu("signal_vci_icu");
    soclib::caba::VciSignals<vci_param> signal_vci_tty("signal_vci_tty");
    soclib::caba::VciSignals<vci_param>
signal_vci_vcimultiram0("signal_vci_vcimultiram0");
    soclib::caba::VciSignals<vci_param>
signal_vci_vcimultiram1("signal_vci_vcimultiram1");
    //    soclib::caba::VciSignals<vci_param>
signal_vci_vcitimer("signal_vci_vcitimer");
    sc_core::sc_signal<bool> signal_xicu_irq;


    // Components

    soclib::common::Loader loader(argv[1]);

    Processor::set_loader(loader);
    //    Processor::setResetAddress(0x80020000);
#if defined(CONFIG_SOCLIB_MEMCHECK)
    Processor::init(maptab, loader, "tty,xicu");
#endif

    soclib::caba::VciXcacheWrapper<vci_param, Processor> *cpu[cpu_count];

    for ( size_t i=0; i<cpu_count; ++i ) {
      std::ostringstream o;
      o << "cpu" << i;
      cpu[i] = new soclib::caba::VciXcacheWrapper<vci_param, Processor>(
               o.str().c_str(), i, maptab,IntTab(i),1, 8, 4, 1, 8, 4);
    }

    //#if defined(CONFIG_GDB_START_FORZEN)
    //    Processor::start_forzen();
    //#endif

    soclib::caba::VciRam<vci_param> vcimultiram0("vcimultiram0", IntTab(0),
maptab, loader);
    soclib::caba::VciRam<vci_param> vcimultiram1("vcimultiram1", IntTab(1),
maptab, loader);
    soclib::caba::VciMultiTty<vci_param> vcitty("vcitty",    IntTab(2), maptab,
"vcitty", NULL);
    soclib::caba::VciXicu<vci_param> vcixicu("vcixicu", maptab, IntTab(3), 2,
1, cpu_count, cpu_count);

    soclib::caba::VciVgmn<vci_param> vgmn("vgmn",maptab, cpu_count, 4, 2, 8);
    //    soclib::caba::VciTimer<vci_param>
vcitimer("vcitimer",IntTab(2),maptab,4);
    //    Net-List
    for ( size_t i=0; i<cpu_count; ++i ) {
      cpu[i]->p_clk(signal_clk);
      cpu[i]->p_resetn(signal_resetn);
      for ( size_t irq=0; irq<Processor::n_irq; ++irq )
        cpu[i]->p_irq[irq](signal_cpu_it[i][irq]);
      vcixicu.p_irq[i](signal_cpu_it[i][0]);
      //  vcitimer.p_vci(signal_vci_vcitimer);
          //vcitimer.p_irq[i](signal_cpu_it[i][0]);
      cpu[i]->p_vci(signal_vci_m[i]);
      vgmn.p_to_initiator[i](signal_vci_m[i]);
    }

    vcimultiram0.p_clk(signal_clk);
    vcimultiram0.p_resetn(signal_resetn);
    vcimultiram0.p_vci(signal_vci_vcimultiram0);

    vcimultiram1.p_clk(signal_clk);
    vcimultiram1.p_resetn(signal_resetn);
    vcimultiram1.p_vci(signal_vci_vcimultiram1);

    vcitty.p_clk(signal_clk);
    vcitty.p_resetn(signal_resetn);
    vcitty.p_vci(signal_vci_tty);
    vcitty.p_irq[0](signal_xicu_irq);

    // vcitimer.p_vci(signal_vci_vcitimer);
    // vcitimer.p_irq[i](signal_cpu_it[i]


    vcixicu.p_clk(signal_clk);
    vcixicu.p_resetn(signal_resetn);
    vcixicu.p_vci(signal_vci_xicu);
    vcixicu.p_hwi[0](signal_xicu_irq);

    vgmn.p_clk(signal_clk);
    vgmn.p_resetn(signal_resetn);
    vgmn.p_to_target[0](signal_vci_vcimultiram0);
    vgmn.p_to_target[1](signal_vci_vcimultiram1);
    vgmn.p_to_target[2](signal_vci_tty);
    vgmn.p_to_target[3](signal_vci_xicu);
    // vgmn.p_to_target[2](signal_vci_vcitimer);

    sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));
    signal_resetn = false;
    sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));
    signal_resetn = true;
    sc_core::sc_start();

    return EXIT_SUCCESS;
}

int sc_main (int argc, char *argv[])
{
    try {
        return _main(argc, argv);
    } catch (std::exception &e) {
        std::cout << e.what() << std::endl;
    } catch (...) {
        std::cout << "Unknown exception occured" << std::endl;
        throw;
    }
    return 1;
}

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[Bug 1001300] problème de commutation des taches

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--- Comment #10 from atef <benhajatef@yahoo.fr> 2011-08-14 02:46:39 BST ---
(In reply to comment #9)
> I fail to operate this platform, I am sending the file top.cc (which contains
> the description of the MIPS architecture) and the file plf_intr.h. This error
> message is displayed during simulation:
> [GDB] CPU0 (cpu0) cycle: ................ PC: bfc0039c FAULT: bad address.
> end I not find words to thank you for your help.
> 
> 
> 
> 
> 
>                             plf_intr.h
> 
> 
> 
> 
> #ifdef CYGONCE_HAL_PLF_INTR_H
> #define CYGONCE_HAL_PLF_INTR_H
> 
> #include <pkgconf/hal.h>
> #include <cyg/infra/cyg_type.h>
> 
> #define HAL_PLATFORM_RESET()              CYG_EMPTY_STATEMENT
> #define HAL_PALTFORM_RESET_ENTRY        0xbfc00000
> 
> #define CYGNUM_HAL_INTERRUPT_RTC  p_irq_in[0]
> 
> 
> /*  code de trois macro*/
> 
> 
> 
> 
> #define CYGHWR_HAL_CLOCK_CONTROL_DEFINE
> #endif
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
>                                       TOP.CC
> 
> 
> #include <iostream>
> #include <cstdlib>
> #include <stdexcept>
> 
> #define CONFIG_GDB_SERVER
> 
> #include "mapping_table.h"
> 
> #if defined(CONFIG_GDB_SERVER)
> # include "gdbserver.h"
> #endif
> 
> #include "vci_xcache_wrapper.h"
> #include "vci_ram.h"
> #include "vci_heterogeneous_rom.h"
> #include "vci_multi_tty.h"
> //#include "vci_timer.h"
> #include "vci_locks.h"
> #include "vci_xicu.h"
> #include "vci_vgmn.h"
> 
> // You may set the SOCLIB_GDB environment variable to
> // START_FROZEN before starting the simulator.
> 
> #include "mips32_vmem.h"
> 
> typedef soclib::common::GdbServer<soclib::common::Mips32El4kpIss> Processor;
> 
> int _main(int argc, char *argv[])
> {
>     // Avoid repeating these everywhere
>     using soclib::common::IntTab;
>     using soclib::common::Segment;
>     size_t cpu_count = 1;
> 
>     if (argc < 2)
>       return 1;
> 
>     // Define our VCI parameters
>     typedef soclib::caba::VciParams<4,9,32,1,1,1,8,1,1,1> vci_param;
>     //   
> soclib::common::GdbServer<soclib::common::Mips32El4kpIss>::start_forzen();
>     // Mapping table
>     soclib::common::MappingTable maptab(32, IntTab(8), IntTab(8), 0x00c00000);
> 
>     maptab.add(Segment("rom",   0x1fc00000, 0x00100000,  IntTab(0), false));
>     maptab.add(Segment("ram" ,  0x80000000, 0x00400000 , IntTab(1), true));
> 
>     maptab.add(Segment("tty"  , 0xc0c00000,  0x10, IntTab(2), false));
>     maptab.add(Segment("xicu",   0xd0c00200, 4096, IntTab(3), false));
>     //  maptab.add(Segment("timer", 0xb0c00000,0x00000100, IntTab(2), false));
> 
>     // Signals
> 
>     sc_core::sc_clock signal_clk("signal_clk");
>     sc_core::sc_signal<bool> signal_resetn("signal_resetn");
> 
>     sc_core::sc_signal<bool> signal_cpu_it[cpu_count][Processor::n_irq]; 
> 
>     soclib::caba::VciSignals<vci_param> signal_vci_m[cpu_count];
> 
>     soclib::caba::VciSignals<vci_param> signal_vci_xicu("signal_vci_icu");
>     soclib::caba::VciSignals<vci_param> signal_vci_tty("signal_vci_tty");
>     soclib::caba::VciSignals<vci_param>
> signal_vci_vcimultiram0("signal_vci_vcimultiram0");
>     soclib::caba::VciSignals<vci_param>
> signal_vci_vcimultiram1("signal_vci_vcimultiram1");
>     //    soclib::caba::VciSignals<vci_param>
> signal_vci_vcitimer("signal_vci_vcitimer");
>     sc_core::sc_signal<bool> signal_xicu_irq;
> 
> 
>     // Components
> 
>     soclib::common::Loader loader(argv[1]);
> 
>     Processor::set_loader(loader);
>     //    Processor::setResetAddress(0x80020000);
> #if defined(CONFIG_SOCLIB_MEMCHECK)
>     Processor::init(maptab, loader, "tty,xicu");
> #endif
> 
>     soclib::caba::VciXcacheWrapper<vci_param, Processor> *cpu[cpu_count];
> 
>     for ( size_t i=0; i<cpu_count; ++i ) {
>       std::ostringstream o;
>       o << "cpu" << i;
>       cpu[i] = new soclib::caba::VciXcacheWrapper<vci_param, Processor>(
>                o.str().c_str(), i, maptab,IntTab(i),1, 8, 4, 1, 8, 4);
>     }
> 
>     //#if defined(CONFIG_GDB_START_FORZEN)
>     //    Processor::start_forzen();
>     //#endif
> 
>     soclib::caba::VciRam<vci_param> vcimultiram0("vcimultiram0", IntTab(0),
> maptab, loader);
>     soclib::caba::VciRam<vci_param> vcimultiram1("vcimultiram1", IntTab(1),
> maptab, loader);
>     soclib::caba::VciMultiTty<vci_param> vcitty("vcitty",    IntTab(2), maptab,
> "vcitty", NULL);
>     soclib::caba::VciXicu<vci_param> vcixicu("vcixicu", maptab, IntTab(3), 2,
> 1, cpu_count, cpu_count);
> 
>     soclib::caba::VciVgmn<vci_param> vgmn("vgmn",maptab, cpu_count, 4, 2, 8);
>     //    soclib::caba::VciTimer<vci_param>
> vcitimer("vcitimer",IntTab(2),maptab,4);
>     //    Net-List
>     for ( size_t i=0; i<cpu_count; ++i ) {
>       cpu[i]->p_clk(signal_clk);
>       cpu[i]->p_resetn(signal_resetn);
>       for ( size_t irq=0; irq<Processor::n_irq; ++irq )
>         cpu[i]->p_irq[irq](signal_cpu_it[i][irq]);
>       vcixicu.p_irq[i](signal_cpu_it[i][0]);
>       //  vcitimer.p_vci(signal_vci_vcitimer);
>           //vcitimer.p_irq[i](signal_cpu_it[i][0]);
>       cpu[i]->p_vci(signal_vci_m[i]);
>       vgmn.p_to_initiator[i](signal_vci_m[i]);
>     }
> 
>     vcimultiram0.p_clk(signal_clk);
>     vcimultiram0.p_resetn(signal_resetn);
>     vcimultiram0.p_vci(signal_vci_vcimultiram0);
> 
>     vcimultiram1.p_clk(signal_clk);
>     vcimultiram1.p_resetn(signal_resetn);
>     vcimultiram1.p_vci(signal_vci_vcimultiram1);
> 
>     vcitty.p_clk(signal_clk);
>     vcitty.p_resetn(signal_resetn);
>     vcitty.p_vci(signal_vci_tty);
>     vcitty.p_irq[0](signal_xicu_irq);
> 
>     // vcitimer.p_vci(signal_vci_vcitimer);
>     // vcitimer.p_irq[i](signal_cpu_it[i]
> 
> 
>     vcixicu.p_clk(signal_clk);
>     vcixicu.p_resetn(signal_resetn);
>     vcixicu.p_vci(signal_vci_xicu);
>     vcixicu.p_hwi[0](signal_xicu_irq);
> 
>     vgmn.p_clk(signal_clk);
>     vgmn.p_resetn(signal_resetn);
>     vgmn.p_to_target[0](signal_vci_vcimultiram0);
>     vgmn.p_to_target[1](signal_vci_vcimultiram1);
>     vgmn.p_to_target[2](signal_vci_tty);
>     vgmn.p_to_target[3](signal_vci_xicu);
>     // vgmn.p_to_target[2](signal_vci_vcitimer);
> 
>     sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));
>     signal_resetn = false;
>     sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));
>     signal_resetn = true;
>     sc_core::sc_start();
> 
>     return EXIT_SUCCESS;
> }
> 
> int sc_main (int argc, char *argv[])
> {
>     try {
>         return _main(argc, argv);
>     } catch (std::exception &e) {
>         std::cout << e.what() << std::endl;
>     } catch (...) {
>         std::cout << "Unknown exception occured" << std::endl;
>         throw;
>     }
>     return 1;
> }

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--- Comment #10 from atef <benhajatef@yahoo.fr> 2011-08-14 02:46:39 BST ---
(In reply to comment #9)
> I fail to operate this platform, I am sending the file top.cc (which contains
> the description of the MIPS architecture) and the file plf_intr.h. This error
> message is displayed during simulation:
> [GDB] CPU0 (cpu0) cycle: ................ PC: bfc0039c FAULT: bad address.
> end I not find words to thank you for your help.
> 
> 
> 
> 
> 
>                             plf_intr.h
> 
> 
> 
> 
> #ifdef CYGONCE_HAL_PLF_INTR_H
> #define CYGONCE_HAL_PLF_INTR_H
> 
> #include <pkgconf/hal.h>
> #include <cyg/infra/cyg_type.h>
> 
> #define HAL_PLATFORM_RESET()              CYG_EMPTY_STATEMENT
> #define HAL_PALTFORM_RESET_ENTRY        0xbfc00000
> 
> #define CYGNUM_HAL_INTERRUPT_RTC  p_irq_in[0]
> 
> 
> /*  code de trois macro*/
> 
> 
> 
> 
> #define CYGHWR_HAL_CLOCK_CONTROL_DEFINE
> #endif
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
>                                       TOP.CC
> 
> 
> #include <iostream>
> #include <cstdlib>
> #include <stdexcept>
> 
> #define CONFIG_GDB_SERVER
> 
> #include "mapping_table.h"
> 
> #if defined(CONFIG_GDB_SERVER)
> # include "gdbserver.h"
> #endif
> 
> #include "vci_xcache_wrapper.h"
> #include "vci_ram.h"
> #include "vci_heterogeneous_rom.h"
> #include "vci_multi_tty.h"
> //#include "vci_timer.h"
> #include "vci_locks.h"
> #include "vci_xicu.h"
> #include "vci_vgmn.h"
> 
> // You may set the SOCLIB_GDB environment variable to
> // START_FROZEN before starting the simulator.
> 
> #include "mips32_vmem.h"
> 
> typedef soclib::common::GdbServer<soclib::common::Mips32El4kpIss> Processor;
> 
> int _main(int argc, char *argv[])
> {
>     // Avoid repeating these everywhere
>     using soclib::common::IntTab;
>     using soclib::common::Segment;
>     size_t cpu_count = 1;
> 
>     if (argc < 2)
>       return 1;
> 
>     // Define our VCI parameters
>     typedef soclib::caba::VciParams<4,9,32,1,1,1,8,1,1,1> vci_param;
>     //   
> soclib::common::GdbServer<soclib::common::Mips32El4kpIss>::start_forzen();
>     // Mapping table
>     soclib::common::MappingTable maptab(32, IntTab(8), IntTab(8), 0x00c00000);
> 
>     maptab.add(Segment("rom",   0x1fc00000, 0x00100000,  IntTab(0), false));
>     maptab.add(Segment("ram" ,  0x80000000, 0x00400000 , IntTab(1), true));
> 
>     maptab.add(Segment("tty"  , 0xc0c00000,  0x10, IntTab(2), false));
>     maptab.add(Segment("xicu",   0xd0c00200, 4096, IntTab(3), false));
>     //  maptab.add(Segment("timer", 0xb0c00000,0x00000100, IntTab(2), false));
> 
>     // Signals
> 
>     sc_core::sc_clock signal_clk("signal_clk");
>     sc_core::sc_signal<bool> signal_resetn("signal_resetn");
> 
>     sc_core::sc_signal<bool> signal_cpu_it[cpu_count][Processor::n_irq]; 
> 
>     soclib::caba::VciSignals<vci_param> signal_vci_m[cpu_count];
> 
>     soclib::caba::VciSignals<vci_param> signal_vci_xicu("signal_vci_icu");
>     soclib::caba::VciSignals<vci_param> signal_vci_tty("signal_vci_tty");
>     soclib::caba::VciSignals<vci_param>
> signal_vci_vcimultiram0("signal_vci_vcimultiram0");
>     soclib::caba::VciSignals<vci_param>
> signal_vci_vcimultiram1("signal_vci_vcimultiram1");
>     //    soclib::caba::VciSignals<vci_param>
> signal_vci_vcitimer("signal_vci_vcitimer");
>     sc_core::sc_signal<bool> signal_xicu_irq;
> 
> 
>     // Components
> 
>     soclib::common::Loader loader(argv[1]);
> 
>     Processor::set_loader(loader);
>     //    Processor::setResetAddress(0x80020000);
> #if defined(CONFIG_SOCLIB_MEMCHECK)
>     Processor::init(maptab, loader, "tty,xicu");
> #endif
> 
>     soclib::caba::VciXcacheWrapper<vci_param, Processor> *cpu[cpu_count];
> 
>     for ( size_t i=0; i<cpu_count; ++i ) {
>       std::ostringstream o;
>       o << "cpu" << i;
>       cpu[i] = new soclib::caba::VciXcacheWrapper<vci_param, Processor>(
>                o.str().c_str(), i, maptab,IntTab(i),1, 8, 4, 1, 8, 4);
>     }
> 
>     //#if defined(CONFIG_GDB_START_FORZEN)
>     //    Processor::start_forzen();
>     //#endif
> 
>     soclib::caba::VciRam<vci_param> vcimultiram0("vcimultiram0", IntTab(0),
> maptab, loader);
>     soclib::caba::VciRam<vci_param> vcimultiram1("vcimultiram1", IntTab(1),
> maptab, loader);
>     soclib::caba::VciMultiTty<vci_param> vcitty("vcitty",    IntTab(2), maptab,
> "vcitty", NULL);
>     soclib::caba::VciXicu<vci_param> vcixicu("vcixicu", maptab, IntTab(3), 2,
> 1, cpu_count, cpu_count);
> 
>     soclib::caba::VciVgmn<vci_param> vgmn("vgmn",maptab, cpu_count, 4, 2, 8);
>     //    soclib::caba::VciTimer<vci_param>
> vcitimer("vcitimer",IntTab(2),maptab,4);
>     //    Net-List
>     for ( size_t i=0; i<cpu_count; ++i ) {
>       cpu[i]->p_clk(signal_clk);
>       cpu[i]->p_resetn(signal_resetn);
>       for ( size_t irq=0; irq<Processor::n_irq; ++irq )
>         cpu[i]->p_irq[irq](signal_cpu_it[i][irq]);
>       vcixicu.p_irq[i](signal_cpu_it[i][0]);
>       //  vcitimer.p_vci(signal_vci_vcitimer);
>           //vcitimer.p_irq[i](signal_cpu_it[i][0]);
>       cpu[i]->p_vci(signal_vci_m[i]);
>       vgmn.p_to_initiator[i](signal_vci_m[i]);
>     }
> 
>     vcimultiram0.p_clk(signal_clk);
>     vcimultiram0.p_resetn(signal_resetn);
>     vcimultiram0.p_vci(signal_vci_vcimultiram0);
> 
>     vcimultiram1.p_clk(signal_clk);
>     vcimultiram1.p_resetn(signal_resetn);
>     vcimultiram1.p_vci(signal_vci_vcimultiram1);
> 
>     vcitty.p_clk(signal_clk);
>     vcitty.p_resetn(signal_resetn);
>     vcitty.p_vci(signal_vci_tty);
>     vcitty.p_irq[0](signal_xicu_irq);
> 
>     // vcitimer.p_vci(signal_vci_vcitimer);
>     // vcitimer.p_irq[i](signal_cpu_it[i]
> 
> 
>     vcixicu.p_clk(signal_clk);
>     vcixicu.p_resetn(signal_resetn);
>     vcixicu.p_vci(signal_vci_xicu);
>     vcixicu.p_hwi[0](signal_xicu_irq);
> 
>     vgmn.p_clk(signal_clk);
>     vgmn.p_resetn(signal_resetn);
>     vgmn.p_to_target[0](signal_vci_vcimultiram0);
>     vgmn.p_to_target[1](signal_vci_vcimultiram1);
>     vgmn.p_to_target[2](signal_vci_tty);
>     vgmn.p_to_target[3](signal_vci_xicu);
>     // vgmn.p_to_target[2](signal_vci_vcitimer);
> 
>     sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));
>     signal_resetn = false;
>     sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));
>     signal_resetn = true;
>     sc_core::sc_start();
> 
>     return EXIT_SUCCESS;
> }
> 
> int sc_main (int argc, char *argv[])
> {
>     try {
>         return _main(argc, argv);
>     } catch (std::exception &e) {
>         std::cout << e.what() << std::endl;
>     } catch (...) {
>         std::cout << "Unknown exception occured" << std::endl;
>         throw;
>     }
>     return 1;
> }

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[Bug 1001300] problème de commutation des taches

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--- Comment #9 from atef <benhajatef@yahoo.fr> 2011-08-08 03:38:15 BST ---
I fail to operate this platform, I am sending the file top.cc (which contains
the description of the MIPS architecture) and the file plf_intr.h. This error
message is displayed during simulation:
[GDB] CPU0 (cpu0) cycle: ................ PC: bfc0039c FAULT: bad address.
end I not find words to thank you for your help.





                            plf_intr.h




#ifdef CYGONCE_HAL_PLF_INTR_H
#define CYGONCE_HAL_PLF_INTR_H

#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>

#define HAL_PLATFORM_RESET()              CYG_EMPTY_STATEMENT
#define HAL_PALTFORM_RESET_ENTRY        0xbfc00000

#define CYGNUM_HAL_INTERRUPT_RTC  p_irq_in[0]


/*  code de trois macro*/




#define CYGHWR_HAL_CLOCK_CONTROL_DEFINE
#endif










                                      TOP.CC


#include <iostream>
#include <cstdlib>
#include <stdexcept>

#define CONFIG_GDB_SERVER

#include "mapping_table.h"

#if defined(CONFIG_GDB_SERVER)
# include "gdbserver.h"
#endif

#include "vci_xcache_wrapper.h"
#include "vci_ram.h"
#include "vci_heterogeneous_rom.h"
#include "vci_multi_tty.h"
//#include "vci_timer.h"
#include "vci_locks.h"
#include "vci_xicu.h"
#include "vci_vgmn.h"

// You may set the SOCLIB_GDB environment variable to
// START_FROZEN before starting the simulator.

#include "mips32_vmem.h"

typedef soclib::common::GdbServer<soclib::common::Mips32El4kpIss> Processor;

int _main(int argc, char *argv[])
{
    // Avoid repeating these everywhere
    using soclib::common::IntTab;
    using soclib::common::Segment;
    size_t cpu_count = 1;

    if (argc < 2)
      return 1;

    // Define our VCI parameters
    typedef soclib::caba::VciParams<4,9,32,1,1,1,8,1,1,1> vci_param;
    //   
soclib::common::GdbServer<soclib::common::Mips32El4kpIss>::start_forzen();
    // Mapping table
    soclib::common::MappingTable maptab(32, IntTab(8), IntTab(8), 0x00c00000);

    maptab.add(Segment("rom",   0x1fc00000, 0x00100000,  IntTab(0), false));
    maptab.add(Segment("ram" ,  0x80000000, 0x00400000 , IntTab(1), true));

    maptab.add(Segment("tty"  , 0xc0c00000,  0x10, IntTab(2), false));
    maptab.add(Segment("xicu",   0xd0c00200, 4096, IntTab(3), false));
    //  maptab.add(Segment("timer", 0xb0c00000,0x00000100, IntTab(2), false));

    // Signals

    sc_core::sc_clock signal_clk("signal_clk");
    sc_core::sc_signal<bool> signal_resetn("signal_resetn");

    sc_core::sc_signal<bool> signal_cpu_it[cpu_count][Processor::n_irq]; 

    soclib::caba::VciSignals<vci_param> signal_vci_m[cpu_count];

    soclib::caba::VciSignals<vci_param> signal_vci_xicu("signal_vci_icu");
    soclib::caba::VciSignals<vci_param> signal_vci_tty("signal_vci_tty");
    soclib::caba::VciSignals<vci_param>
signal_vci_vcimultiram0("signal_vci_vcimultiram0");
    soclib::caba::VciSignals<vci_param>
signal_vci_vcimultiram1("signal_vci_vcimultiram1");
    //    soclib::caba::VciSignals<vci_param>
signal_vci_vcitimer("signal_vci_vcitimer");
    sc_core::sc_signal<bool> signal_xicu_irq;


    // Components

    soclib::common::Loader loader(argv[1]);

    Processor::set_loader(loader);
    //    Processor::setResetAddress(0x80020000);
#if defined(CONFIG_SOCLIB_MEMCHECK)
    Processor::init(maptab, loader, "tty,xicu");
#endif

    soclib::caba::VciXcacheWrapper<vci_param, Processor> *cpu[cpu_count];

    for ( size_t i=0; i<cpu_count; ++i ) {
      std::ostringstream o;
      o << "cpu" << i;
      cpu[i] = new soclib::caba::VciXcacheWrapper<vci_param, Processor>(
               o.str().c_str(), i, maptab,IntTab(i),1, 8, 4, 1, 8, 4);
    }

    //#if defined(CONFIG_GDB_START_FORZEN)
    //    Processor::start_forzen();
    //#endif

    soclib::caba::VciRam<vci_param> vcimultiram0("vcimultiram0", IntTab(0),
maptab, loader);
    soclib::caba::VciRam<vci_param> vcimultiram1("vcimultiram1", IntTab(1),
maptab, loader);
    soclib::caba::VciMultiTty<vci_param> vcitty("vcitty",    IntTab(2), maptab,
"vcitty", NULL);
    soclib::caba::VciXicu<vci_param> vcixicu("vcixicu", maptab, IntTab(3), 2,
1, cpu_count, cpu_count);

    soclib::caba::VciVgmn<vci_param> vgmn("vgmn",maptab, cpu_count, 4, 2, 8);
    //    soclib::caba::VciTimer<vci_param>
vcitimer("vcitimer",IntTab(2),maptab,4);
    //    Net-List
    for ( size_t i=0; i<cpu_count; ++i ) {
      cpu[i]->p_clk(signal_clk);
      cpu[i]->p_resetn(signal_resetn);
      for ( size_t irq=0; irq<Processor::n_irq; ++irq )
        cpu[i]->p_irq[irq](signal_cpu_it[i][irq]);
      vcixicu.p_irq[i](signal_cpu_it[i][0]);
      //  vcitimer.p_vci(signal_vci_vcitimer);
          //vcitimer.p_irq[i](signal_cpu_it[i][0]);
      cpu[i]->p_vci(signal_vci_m[i]);
      vgmn.p_to_initiator[i](signal_vci_m[i]);
    }

    vcimultiram0.p_clk(signal_clk);
    vcimultiram0.p_resetn(signal_resetn);
    vcimultiram0.p_vci(signal_vci_vcimultiram0);

    vcimultiram1.p_clk(signal_clk);
    vcimultiram1.p_resetn(signal_resetn);
    vcimultiram1.p_vci(signal_vci_vcimultiram1);

    vcitty.p_clk(signal_clk);
    vcitty.p_resetn(signal_resetn);
    vcitty.p_vci(signal_vci_tty);
    vcitty.p_irq[0](signal_xicu_irq);

    // vcitimer.p_vci(signal_vci_vcitimer);
    // vcitimer.p_irq[i](signal_cpu_it[i]


    vcixicu.p_clk(signal_clk);
    vcixicu.p_resetn(signal_resetn);
    vcixicu.p_vci(signal_vci_xicu);
    vcixicu.p_hwi[0](signal_xicu_irq);

    vgmn.p_clk(signal_clk);
    vgmn.p_resetn(signal_resetn);
    vgmn.p_to_target[0](signal_vci_vcimultiram0);
    vgmn.p_to_target[1](signal_vci_vcimultiram1);
    vgmn.p_to_target[2](signal_vci_tty);
    vgmn.p_to_target[3](signal_vci_xicu);
    // vgmn.p_to_target[2](signal_vci_vcitimer);

    sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));
    signal_resetn = false;
    sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));
    signal_resetn = true;
    sc_core::sc_start();

    return EXIT_SUCCESS;
}

int sc_main (int argc, char *argv[])
{
    try {
        return _main(argc, argv);
    } catch (std::exception &e) {
        std::cout << e.what() << std::endl;
    } catch (...) {
        std::cout << "Unknown exception occured" << std::endl;
        throw;
    }
    return 1;
}

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--- Comment #8 from Christophe Coutand <ecos@hotmail.co.uk> 2011-08-07 05:16:32 BST ---
In the plf_intr.h of the soclib package, you can overwrite the clock definition
provided from the hal_intr.h.

You must select the correct interrupt for the RTC clock:

#define CYGNUM_HAL_INTERRUPT_RTC YOUR_SOCLIB_TIMER_IRQ_NUM

and define the 3 macos used by eCos to access the clock:

externC CYG_WORD32 cyg_hal_clock_period;
#define CYGHWR_HAL_CLOCK_PERIOD_DEFINED

#define HAL_CLOCK_INITIALIZE( _period_ )           \
CYG_MACRO_START                                           \
     /* Place code here * /
    cyg_hal_clock_period = _period_;                       \
CYG_MACRO_END

#define HAL_CLOCK_RESET( _vector_, _period_ )   \
     /* Place code here * /
CYG_MACRO_END

#define HAL_CLOCK_READ( _pvalue_ )                 \
CYG_MACRO_START                                           \
     /* Place code here * /
CYG_MACRO_END

#define CYGHWR_HAL_CLOCK_CONTROL_DEFINED

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--- Comment #7 from atef <benhajatef@yahoo.fr> 2011-08-07 04:39:23 BST ---
Thank you again,
how can i implement the eCos RTC clock using the vci-xicu, it must change the
file hal_intr.h, or the patch soclib.

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--- Comment #6 from Christophe Coutand <ecos@hotmail.co.uk> 2011-08-06 18:22:20 BST ---
When browsing the MIPS32 architecture of SoClib, i can't see that the
coprocessor 0 count / compare registers are triggering interrupts. You should
check that by asking on the SoClib mailing list.

As a workaround, you can implement the eCos RTC clock using the vci-xicu timer
instead.

BTW, could you provide the ecos.ecc you are using to build eCos?

Christophe

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--- Comment #4 from atef <benhajatef@yahoo.fr> 2011-08-04 05:16:27 BST ---
First of all I want to thank you for your help. Here is a description of the
architecture that I used and debugger.
 GdbServer tool is a software debugger for SocLib. It listens for TCP
connection from Gnu GDB clients :GNU gdb 7.0 
platform mips32_soclib contains:
 *processor mips32 : It implements all instructions defined in the MIPS32
architecture specification, with the following limitations:
The floating point instructions are supported, FPU exception detection is
partially implemented
The Mips virtual memory instructions are not supported. The MMU is implemented
as an external TLB (SoCLib generic).
Both little-endian and big-endian implementations are available.
Mips defines 6 interrupts lines. The handling and prioritization of the
interrupts is deferred to software
 *VciXicu:  memory mapped Hardware interrupt + Timer + IPI controller 
 *Segment of Ram

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--- Comment #4 from atef <benhajatef@yahoo.fr> 2011-08-04 05:16:27 BST ---
First of all I want to thank you for your help. Here is a description of the
architecture that I used and debugger.
 GdbServer tool is a software debugger for SocLib. It listens for TCP
connection from Gnu GDB clients :GNU gdb 7.0 
platform mips32_soclib contains:
 *processor mips32 : It implements all instructions defined in the MIPS32
architecture specification, with the following limitations:
The floating point instructions are supported, FPU exception detection is
partially implemented
The Mips virtual memory instructions are not supported. The MMU is implemented
as an external TLB (SoCLib generic).
Both little-endian and big-endian implementations are available.
Mips defines 6 interrupts lines. The handling and prioritization of the
interrupts is deferred to software
 *VciXicu:  memory mapped Hardware interrupt + Timer + IPI controller 
 *Segment of Ram

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--- Comment #5 from atef <benhajatef@yahoo.fr> 2011-08-05 13:06:45 BST ---
(In reply to comment #4)
> First of all I want to thank you for your help. Here is a description of the
> architecture that I used and debugger.
>  GdbServer tool is a software debugger for SocLib. It listens for TCP
> connection from Gnu GDB clients :GNU gdb 7.0 
> platform mips32_soclib contains:
>  *processor mips32 : It implements all instructions defined in the MIPS32
> architecture specification, with the following limitations:
> The floating point instructions are supported, FPU exception detection is
> partially implemented
> The Mips virtual memory instructions are not supported. The MMU is implemented
> as an external TLB (SoCLib generic).
> Both little-endian and big-endian implementations are available.
> Mips defines 6 interrupts lines. The handling and prioritization of the
> interrupts is deferred to software
>  *VciXicu:  memory mapped Hardware interrupt + Timer + IPI controller 
>  *Segment of Ram

(In reply to comment #4)
> First of all I want to thank you for your help. Here is a description of the
> architecture that I used and debugger.
>  GdbServer tool is a software debugger for SocLib. It listens for TCP
> connection from Gnu GDB clients :GNU gdb 7.0 
> platform mips32_soclib contains:
>  *processor mips32 : It implements all instructions defined in the MIPS32
> architecture specification, with the following limitations:
> The floating point instructions are supported, FPU exception detection is
> partially implemented
> The Mips virtual memory instructions are not supported. The MMU is implemented
> as an external TLB (SoCLib generic).
> Both little-endian and big-endian implementations are available.
> Mips defines 6 interrupts lines. The handling and prioritization of the
> interrupts is deferred to software
>  *VciXicu:  memory mapped Hardware interrupt + Timer + IPI controller 
>  *Segment of Ram

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--- Comment #5 from atef <benhajatef@yahoo.fr> 2011-08-05 13:06:45 BST ---
(In reply to comment #4)
> First of all I want to thank you for your help. Here is a description of the
> architecture that I used and debugger.
>  GdbServer tool is a software debugger for SocLib. It listens for TCP
> connection from Gnu GDB clients :GNU gdb 7.0 
> platform mips32_soclib contains:
>  *processor mips32 : It implements all instructions defined in the MIPS32
> architecture specification, with the following limitations:
> The floating point instructions are supported, FPU exception detection is
> partially implemented
> The Mips virtual memory instructions are not supported. The MMU is implemented
> as an external TLB (SoCLib generic).
> Both little-endian and big-endian implementations are available.
> Mips defines 6 interrupts lines. The handling and prioritization of the
> interrupts is deferred to software
>  *VciXicu:  memory mapped Hardware interrupt + Timer + IPI controller 
>  *Segment of Ram

(In reply to comment #4)
> First of all I want to thank you for your help. Here is a description of the
> architecture that I used and debugger.
>  GdbServer tool is a software debugger for SocLib. It listens for TCP
> connection from Gnu GDB clients :GNU gdb 7.0 
> platform mips32_soclib contains:
>  *processor mips32 : It implements all instructions defined in the MIPS32
> architecture specification, with the following limitations:
> The floating point instructions are supported, FPU exception detection is
> partially implemented
> The Mips virtual memory instructions are not supported. The MMU is implemented
> as an external TLB (SoCLib generic).
> Both little-endian and big-endian implementations are available.
> Mips defines 6 interrupts lines. The handling and prioritization of the
> interrupts is deferred to software
>  *VciXicu:  memory mapped Hardware interrupt + Timer + IPI controller 
>  *Segment of Ram

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--- Comment #6 from Christophe Coutand <ecos@hotmail.co.uk> 2011-08-06 18:22:20 BST ---
When browsing the MIPS32 architecture of SoClib, i can't see that the
coprocessor 0 count / compare registers are triggering interrupts. You should
check that by asking on the SoClib mailing list.

As a workaround, you can implement the eCos RTC clock using the vci-xicu timer
instead.

BTW, could you provide the ecos.ecc you are using to build eCos?

Christophe

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[Bug 1001300] problème de commutation des taches

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--- Comment #3 from Christophe Coutand <ecos@hotmail.co.uk> 2011-08-03 01:50:54 BST ---
I don't know enough about the MIPS architecture to give you pointers. What type
of debugging facility do you have with the simulator? Can you set breakpoints
for debugging? If you get interrupts, you should hit the
__default_interrupt_vsr function call. The RTC clock is default mapped as
following:

Look inside packages\hal\mips\arch\current\include\hal_intr.h:

// The vector used by the Real time clock. The default here is to use
// interrupt 5, which is connected to the counter/comparator registers
// in many MIPS variants.

#ifndef CYGNUM_HAL_INTERRUPT_RTC
#define CYGNUM_HAL_INTERRUPT_RTC            CYGNUM_HAL_INTERRUPT_5
#endif

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--- Comment #2 from atef <benhajatef@yahoo.fr> 2011-08-02 14:37:56 BST ---
(In reply to comment #1)
> Can you tell if the application crashes? Is the simulator correctly handling
> the interrupt that is used for the kernel RTC? if not, the threads will never
> go behind the cyg_thread_delay() call.
> 
> Christophe

how we can test the simulator correctly handling the interrupt ??

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